From patchwork Tue Apr 19 09:22:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 717551 X-Patchwork-Delegate: tomi.valkeinen@nokia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3J9N5Ej020225 for ; Tue, 19 Apr 2011 09:23:05 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754477Ab1DSJXD (ORCPT ); Tue, 19 Apr 2011 05:23:03 -0400 Received: from na3sys009aog110.obsmtp.com ([74.125.149.203]:39233 "EHLO na3sys009aog110.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754432Ab1DSJXA (ORCPT ); Tue, 19 Apr 2011 05:23:00 -0400 Received: from mail-ey0-f179.google.com ([209.85.215.179]) (using TLSv1) by na3sys009aob110.postini.com ([74.125.148.12]) with SMTP ID DSNKTa1UcoLheo0Eoa7s2aOjYi9lS7ncBKEf@postini.com; Tue, 19 Apr 2011 02:22:59 PDT Received: by mail-ey0-f179.google.com with SMTP id 5so1739187eyg.38 for ; Tue, 19 Apr 2011 02:22:52 -0700 (PDT) Received: by 10.213.28.194 with SMTP id n2mr377189ebc.2.1303204972328; Tue, 19 Apr 2011 02:22:52 -0700 (PDT) Received: from deskari (a62-248-131-233.elisa-laajakaista.fi [62.248.131.233]) by mx.google.com with ESMTPS id m55sm4672311eei.8.2011.04.19.02.22.50 (version=SSLv3 cipher=OTHER); Tue, 19 Apr 2011 02:22:50 -0700 (PDT) From: Tomi Valkeinen To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org Cc: Tomi Valkeinen Subject: [PATCH 10/19] OMAP: DSS2: DSI: wait for TXCLKESC domain to come out of reset Date: Tue, 19 Apr 2011 12:22:13 +0300 Message-Id: <1303204942-25450-11-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1303204942-25450-1-git-send-email-tomi.valkeinen@ti.com> References: <1303204942-25450-1-git-send-email-tomi.valkeinen@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 19 Apr 2011 09:23:06 +0000 (UTC) Add dsi_cio_wait_tx_clk_esc_reset() function which waits for the TXCLKESC domains to come out of reset. Things have worked fine without this, but better be safe than sorry. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 65 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 65 insertions(+), 0 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 9f450af..8d85635 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -1969,6 +1969,65 @@ static void dsi_cio_disable_lane_override(void) REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */ } +static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev) +{ + int t; + int bits[3]; + bool in_use[3]; + + if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { + bits[0] = 28; + bits[1] = 27; + bits[2] = 26; + } else { + bits[0] = 24; + bits[1] = 25; + bits[2] = 26; + } + + in_use[0] = false; + in_use[1] = false; + in_use[2] = false; + + if (dssdev->phy.dsi.clk_lane != 0) + in_use[dssdev->phy.dsi.clk_lane - 1] = true; + if (dssdev->phy.dsi.data1_lane != 0) + in_use[dssdev->phy.dsi.data1_lane - 1] = true; + if (dssdev->phy.dsi.data2_lane != 0) + in_use[dssdev->phy.dsi.data2_lane - 1] = true; + + t = 100000; + while (true) { + u32 l; + int i; + int ok; + + l = dsi_read_reg(DSI_DSIPHY_CFG5); + + ok = 0; + for (i = 0; i < 3; ++i) { + if (!in_use[i] || (l & (1 << bits[i]))) + ok++; + } + + if (ok == 3) + break; + + if (--t == 0) { + for (i = 0; i < 3; ++i) { + if (!in_use[i] || (l & (1 << bits[i]))) + continue; + + DSSERR("CIO TXCLKESC%d domain not coming " \ + "out of reset\n", i); + } + return -EIO; + } + } + + return 0; +} + static int dsi_cio_init(struct omap_dss_device *dssdev) { int r; @@ -2028,6 +2087,10 @@ static int dsi_cio_init(struct omap_dss_device *dssdev) dsi_if_enable(false); REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ + r = dsi_cio_wait_tx_clk_esc_reset(dssdev); + if (r) + goto err_tx_clk_esc_rst; + if (dsi.ulps_enabled) { /* Keep Mark-1 state for 1ms (as per DSI spec) */ ktime_t wait = ns_to_ktime(1000 * 1000); @@ -2050,6 +2113,8 @@ static int dsi_cio_init(struct omap_dss_device *dssdev) return 0; +err_tx_clk_esc_rst: + REG_FLD_MOD(DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ err_cio_pwr_dom: dsi_cio_power(DSI_COMPLEXIO_POWER_OFF); err_cio_pwr: