From patchwork Fri Apr 22 11:08:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: charu@ti.com X-Patchwork-Id: 726951 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3MB5Ccg028390 for ; Fri, 22 Apr 2011 11:05:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755203Ab1DVLFJ (ORCPT ); Fri, 22 Apr 2011 07:05:09 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:38710 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755160Ab1DVLFD (ORCPT ); Fri, 22 Apr 2011 07:05:03 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p3MB4biL001563 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 22 Apr 2011 06:04:39 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p3MB4XMq028986; Fri, 22 Apr 2011 16:34:36 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Fri, 22 Apr 2011 16:34:16 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with SMTP id p3MB4XdM021584; Fri, 22 Apr 2011 16:34:33 +0530 (IST) Received: from x0084895-pc (unknown [10.24.244.78]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id BDF9615800B; Fri, 22 Apr 2011 16:34:30 +0530 (IST) From: Charulatha V To: , CC: , , , Charulatha V Subject: [RFC PATCH 09/18] OMAP: GPIO: cleanup gpio_irq_handler Date: Fri, 22 Apr 2011 16:38:23 +0530 Message-ID: <1303470512-19671-10-git-send-email-charu@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1303470512-19671-1-git-send-email-charu@ti.com> References: <1303470512-19671-1-git-send-email-charu@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 22 Apr 2011 11:05:12 +0000 (UTC) Remove CONFIG_ARCH_OMAP* checks from gpio_irq_handler. Also correct the multi-line comment style in the gpio_irq_handler. Signed-off-by: Charulatha V --- arch/arm/plat-omap/gpio.c | 70 +++++++++++++++++--------------------------- 1 files changed, 27 insertions(+), 43 deletions(-) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 28f58c6..5fe6dbf 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -761,7 +761,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) */ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { - void __iomem *isr_reg = NULL; + u32 isr_val; u32 isr; unsigned int gpio_irq, gpio_index; struct gpio_bank *bank; @@ -771,58 +771,41 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) desc->irq_data.chip->irq_ack(&desc->irq_data); bank = irq_get_handler_data(irq); -#ifdef CONFIG_ARCH_OMAP1 - if (bank->method == METHOD_MPUIO) - isr_reg = bank->base + - OMAP_MPUIO_GPIO_INT / bank->stride; -#endif -#ifdef CONFIG_ARCH_OMAP15XX - if (bank->method == METHOD_GPIO_1510) - isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; -#endif -#if defined(CONFIG_ARCH_OMAP16XX) - if (bank->method == METHOD_GPIO_1610) - isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; -#endif -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - if (bank->method == METHOD_GPIO_7XX) - isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; -#endif -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - if (bank->method == METHOD_GPIO_24XX) - isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; -#endif -#if defined(CONFIG_ARCH_OMAP4) - if (bank->method == METHOD_GPIO_44XX) - isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; -#endif - - if (WARN_ON(!isr_reg)) - goto exit; while(1) { u32 isr_saved, level_mask = 0; u32 enabled; + if (bank->method == METHOD_MPUIO) + isr_val = gpio_mpuio_read(bank->base, + OMAP_MPUIO_GPIO_INT / bank->stride); + else + isr_val = gpio_fn.gpio_read(bank->base, IRQSTATUS_REG0); + enabled = _get_gpio_irqbank_mask(bank); - isr_saved = isr = __raw_readl(isr_reg) & enabled; + isr = isr_val & enabled; + isr_saved = isr; - if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) + /* Common for all MPUIO banks */ + if (bank->method == METHOD_MPUIO) isr &= 0x0000ffff; - if (cpu_class_is_omap2()) { + if (bank->method >= METHOD_GPIO_24XX) level_mask = bank->level_mask & enabled; - } - /* clear edge sensitive interrupts before handler(s) are - called so that we don't miss any interrupt occurred while - executing them */ + /* + * clear edge sensitive interrupts before handler(s) are + * called so that we don't miss any interrupt occurred + * while executing them + */ _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); _clear_gpio_irqbank(bank, isr_saved & ~level_mask); _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); - /* if there is only edge sensitive GPIO pin interrupts - configured, we could unmask GPIO bank interrupt immediately */ + /* + * if there is only edge sensitive GPIO pin interrupts + * configured, we could unmask GPIO bank interrupt immediately + */ if (!level_mask && !unmasked) { unmasked = 1; desc->irq_data.chip->irq_unmask(&desc->irq_data); @@ -853,11 +836,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(gpio_irq); } } - /* if bank has any level sensitive GPIO pin interrupt - configured, we must unmask the bank interrupt only after - handler(s) are executed in order to avoid spurious bank - interrupt */ -exit: + /* + * if bank has any level sensitive GPIO pin interrupt + * configured, we must unmask the bank interrupt only after + * handler(s) are executed in order to avoid spurious bank + * interrupt + */ if (!unmasked) desc->irq_data.chip->irq_unmask(&desc->irq_data); }