From patchwork Thu May 26 01:56:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 819132 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p4Q1vHoQ023566 for ; Thu, 26 May 2011 01:57:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757295Ab1EZB5Q (ORCPT ); Wed, 25 May 2011 21:57:16 -0400 Received: from na3sys009aog115.obsmtp.com ([74.125.149.238]:50361 "EHLO na3sys009aog115.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757276Ab1EZB5Q (ORCPT ); Wed, 25 May 2011 21:57:16 -0400 Received: from mail-gx0-f173.google.com ([209.85.161.173]) (using TLSv1) by na3sys009aob115.postini.com ([74.125.148.12]) with SMTP ID DSNKTd2ze/EuKsEgBWr2yawOtG3U4vKkgScc@postini.com; Wed, 25 May 2011 18:57:15 PDT Received: by gxk26 with SMTP id 26so142003gxk.18 for ; Wed, 25 May 2011 18:57:15 -0700 (PDT) Received: by 10.151.15.16 with SMTP id s16mr405716ybi.54.1306375034852; Wed, 25 May 2011 18:57:14 -0700 (PDT) Received: from localhost (dragon.ti.com [192.94.94.33]) by mx.google.com with ESMTPS id d3sm209436ybi.5.2011.05.25.18.57.12 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 25 May 2011 18:57:13 -0700 (PDT) From: Nishanth Menon To: linux-omap Cc: Moiz Sonasath , Nishanth Menon Subject: [RFC][PATCH 3/9] OMAP4460: HWMOD: DO not reset GPIO1 during HWMOD init Date: Wed, 25 May 2011 18:56:50 -0700 Message-Id: <1306375016-707-4-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1306375016-707-1-git-send-email-nm@ti.com> References: <1306375016-707-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 26 May 2011 01:57:17 +0000 (UTC) From: Moiz Sonasath For OMAP4460, GPIO-7 of bank1 is used for controling the TPS modes, hence GPIO1 should not be reset during init as reset will cause the TPS voltage to drop to 0.9 V. Originally from: http://git.omapzoom.org/?p=kernel/omap.git;a=commitdiff;h=52ae4f0de03b17c064d9ce90a580230f1a596ec1 [nm@ti.com: upstream version] Signed-off-by: Nishanth Menon Signed-off-by: Moiz Sonasath --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 27 ++++++++++++++++++++++++--- 1 files changed, 24 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 2f51a5a..27319c4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1745,7 +1745,7 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, }; -static struct omap_hwmod omap44xx_gpio1_hwmod = { +static struct omap_hwmod omap443x_gpio1_hwmod = { .name = "gpio1", .class = &omap44xx_gpio_hwmod_class, .mpu_irqs = omap44xx_gpio1_irqs, @@ -1761,7 +1761,27 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { .dev_attr = &gpio_dev_attr, .slaves = omap44xx_gpio1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct omap_hwmod omap446x_gpio1_hwmod = { + .name = "gpio1", + .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_gpio1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), + .main_clk = "gpio1_ick", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + }, + }, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .dev_attr = &gpio_dev_attr, + .slaves = omap44xx_gpio1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4460), }; /* gpio2 */ @@ -5079,7 +5099,8 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_dss_venc_hwmod, /* gpio class */ - &omap44xx_gpio1_hwmod, + &omap443x_gpio1_hwmod, + &omap446x_gpio1_hwmod, &omap44xx_gpio2_hwmod, &omap44xx_gpio3_hwmod, &omap44xx_gpio4_hwmod,