From patchwork Tue Jun 7 02:16:05 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 855122 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p572FeQS025132 for ; Tue, 7 Jun 2011 02:18:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756747Ab1FGCQZ (ORCPT ); Mon, 6 Jun 2011 22:16:25 -0400 Received: from na3sys009aog104.obsmtp.com ([74.125.149.73]:39294 "EHLO na3sys009aog104.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756655Ab1FGCQY (ORCPT ); Mon, 6 Jun 2011 22:16:24 -0400 Received: from mail-yi0-f49.google.com ([209.85.218.49]) (using TLSv1) by na3sys009aob104.postini.com ([74.125.148.12]) with SMTP ID DSNKTe2J+PebZI0SHfdAGtQsAMrsZCsIGH0G@postini.com; Mon, 06 Jun 2011 19:16:24 PDT Received: by mail-yi0-f49.google.com with SMTP id 12so364633yie.36 for ; Mon, 06 Jun 2011 19:16:24 -0700 (PDT) Received: by 10.150.190.3 with SMTP id n3mr4872216ybf.67.1307412979752; Mon, 06 Jun 2011 19:16:19 -0700 (PDT) Received: from localhost (dragon.ti.com [192.94.94.33]) by mx.google.com with ESMTPS id w70sm7729yhl.17.2011.06.06.19.16.18 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 06 Jun 2011 19:16:18 -0700 (PDT) From: Nishanth Menon To: linux-omap Cc: kevin , Nishanth Menon Subject: [pm-wip/voltdm_nm][PATCH 02/10] OMAP4: PM: VC: allow channels use of default channel i2c_slaveaddr Date: Mon, 6 Jun 2011 21:16:05 -0500 Message-Id: <1307412972-25854-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1307412972-25854-1-git-send-email-nm@ti.com> References: <1307412972-25854-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 07 Jun 2011 02:18:36 +0000 (UTC) OMAP4's PRM_VC_CFG_CHANNEL register allows for flexibility of configuring for various PMIC configurations. In combinations where the same slave address is used for all domains, it is possible to setup the VC channel for the dependent channels to use the same slave address as the default channel. Since I2C addressing could be 7 bit or 11 bits as per the I2C specification, we use the BIT(15) to flag that this should use the default channel's configuration. Depending on the PMIC and platform used, this can be populated on the PMIC's datastructure and percolates to VC's configuration. Signed-off-by: Nishanth Menon --- arch/arm/mach-omap2/vc.c | 18 ++++++++++++++---- arch/arm/mach-omap2/vc.h | 2 +- arch/arm/mach-omap2/voltage.h | 11 ++++++++++- 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index aa9f0bc..0c0e416 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -309,11 +309,21 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm) vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr; vc->setup_time = voltdm->pmic->volt_setup_time; + if ((vc->flags & OMAP_VC_CHANNEL_DEFAULT) && + (vc->i2c_slave_addr == USE_DEFAULT_CHANNEL_I2C_PARAM)) { + pr_err("%s: voltdm %s: default channel " + "bad config-sa=%2x ?\n", __func__, voltdm->name, + vc->i2c_slave_addr); + return; + } + /* Configure the i2c slave address for this VC */ - voltdm->rmw(vc->smps_sa_mask, - vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), - vc->common->smps_sa_reg); - vc->cfg_channel |= vc_cfg_bits->sa; + if (vc->i2c_slave_addr != USE_DEFAULT_CHANNEL_I2C_PARAM) { + voltdm->rmw(vc->smps_sa_mask, + vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), + vc->common->smps_sa_reg); + vc->cfg_channel |= vc_cfg_bits->sa; + } /* * Configure the PMIC register addresses. diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h index e16dacf..22c0060 100644 --- a/arch/arm/mach-omap2/vc.h +++ b/arch/arm/mach-omap2/vc.h @@ -77,7 +77,7 @@ struct omap_vc_channel { u8 flags; /* channel state */ - u8 i2c_slave_addr; + u16 i2c_slave_addr; u8 volt_reg_addr; u8 cmd_reg_addr; u8 cfg_channel; diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index f079167..1732258 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -109,6 +109,15 @@ struct omap_volt_data { u8 vp_errgain; }; +/* + * Introduced in OMAP4, is a concept of a default channel - in OMAP4, this + * channel is MPU, all other domains such as IVA/CORE, could optionally + * link their i2c reg configuration to use MPU channel's configuration if + * required. To do this, mark in the PMIC structure's + * i2c_slave_addr with this macro. + */ +#define USE_DEFAULT_CHANNEL_I2C_PARAM 0x8000 + /** * struct omap_voltdm_pmic - PMIC specific data required by voltage driver. * @slew_rate: PMIC slew rate (in uv/us) @@ -132,7 +141,7 @@ struct omap_voltdm_pmic { u8 vp_vddmin; u8 vp_vddmax; u8 vp_timeout_us; - u8 i2c_slave_addr; + u16 i2c_slave_addr; u8 volt_reg_addr; u8 cmd_reg_addr; bool i2c_high_speed;