| Message ID | 1307429547.1858.10.camel@deskari (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Tomi Valkeinen |
| Headers | show |
On Tue, 2011-06-07 at 09:52 +0300, Tomi Valkeinen wrote: > On Mon, 2011-06-06 at 17:28 +0200, Cousson, Benoit wrote: > > > Before doing that, could you maybe just try something to make OMAP4 > > looks a little bit more like OMAP3? > > > > dss_fck -> ick > > dss_dss_fck -> main_clk > > > > That should ensure that both modulemode and the PRCM fclk will be > > managed by pm_runtime. > > I made the changes as you suggested, and while I haven't made the > changes to omapdss yet to see if I can remove the dispc_runtime_get/put > style function, I can boot up and start the dss. > > However, after booting up but before enabling the dss driver, I can see > that the clock counts are: > > dss_tv_clk 0 > dss_sys_clk 0 > dss_fck 7 > dss_dss_clk 0 > dss_48mhz_clk 0 > > So the modulemode is set for all dss hwmods? Isn't this exactly how it's > _not_ meant to be, as modulemode should be set only after enabling the > fck? This also seems to keep the DSS from going to RET or OFF, at least in the TI internal PM testing tree. So is the PM side buggy there, and it shouldn't care about the modulemode being enabled if other clocks are off, or is it the hwmod side that's buggy, and it should disable the modulemode also? Tomi -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 6/7/2011 8:52 AM, Valkeinen, Tomi wrote: > On Mon, 2011-06-06 at 17:28 +0200, Cousson, Benoit wrote: > >> Before doing that, could you maybe just try something to make OMAP4 >> looks a little bit more like OMAP3? >> >> dss_fck -> ick >> dss_dss_fck -> main_clk >> >> That should ensure that both modulemode and the PRCM fclk will be >> managed by pm_runtime. > > I made the changes as you suggested, and while I haven't made the > changes to omapdss yet to see if I can remove the dispc_runtime_get/put > style function, I can boot up and start the dss. > > However, after booting up but before enabling the dss driver, I can see > that the clock counts are: > > dss_tv_clk 0 > dss_sys_clk 0 > dss_fck 7 > dss_dss_clk 0 > dss_48mhz_clk 0 > > So the modulemode is set for all dss hwmods? Isn't this exactly how it's > _not_ meant to be, as modulemode should be set only after enabling the > fck? The issue is that there is only one modulemode for the whole DSS. Potentially only the dss_hwmod should have it. But then you have to ensure that this device is enabled before any other DSS devices. If you cannot do that at your level, we will have to set a hwmod dependency between DSS modules and the main DSS subsystem. For the moment we do not have such HW dependencies. Benoit > > Tomi > > > diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c > index b374cd0..d7d86b6 100644 > --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c > +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c > @@ -1133,7 +1133,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { > static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { > .master =&omap44xx_l3_main_2_hwmod, > .slave =&omap44xx_dss_hwmod, > - .clk = "l3_div_ck", > + .clk = "dss_fck", > .addr = omap44xx_dss_dma_addrs, > .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs), > .user = OCP_USER_SDMA, > @@ -1170,7 +1170,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = { > static struct omap_hwmod omap44xx_dss_hwmod = { > .name = "dss_core", > .class =&omap44xx_dss_hwmod_class, > - .main_clk = "dss_fck", > + .main_clk = "dss_dss_clk", > .prcm = { > .omap4 = { > .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, > @@ -1230,7 +1230,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { > static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { > .master =&omap44xx_l3_main_2_hwmod, > .slave =&omap44xx_dss_dispc_hwmod, > - .clk = "l3_div_ck", > + .clk = "dss_fck", > .addr = omap44xx_dss_dispc_dma_addrs, > .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs), > .user = OCP_USER_SDMA, > @@ -1279,7 +1279,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { > .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs), > .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, > .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs), > - .main_clk = "dss_fck", > + .main_clk = "dss_dss_clk", > .prcm = { > .omap4 = { > .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, > @@ -1335,7 +1335,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { > static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { > .master =&omap44xx_l3_main_2_hwmod, > .slave =&omap44xx_dss_dsi1_hwmod, > - .clk = "l3_div_ck", > + .clk = "dss_fck", > .addr = omap44xx_dss_dsi1_dma_addrs, > .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs), > .user = OCP_USER_SDMA, > @@ -1377,7 +1377,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { > .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs), > .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, > .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs), > - .main_clk = "dss_fck", > + .main_clk = "dss_dss_clk", > .prcm = { > .omap4 = { > .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, > @@ -1412,7 +1412,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { > static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { > .master =&omap44xx_l3_main_2_hwmod, > .slave =&omap44xx_dss_dsi2_hwmod, > - .clk = "l3_div_ck", > + .clk = "dss_fck", > .addr = omap44xx_dss_dsi2_dma_addrs, > .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs), > .user = OCP_USER_SDMA, > @@ -1449,7 +1449,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { > .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs), > .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, > .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs), > - .main_clk = "dss_fck", > + .main_clk = "dss_dss_clk", > .prcm = { > .omap4 = { > .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, > @@ -1502,7 +1502,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { > static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { > .master =&omap44xx_l3_main_2_hwmod, > .slave =&omap44xx_dss_hdmi_hwmod, > - .clk = "l3_div_ck", > + .clk = "dss_fck", > .addr = omap44xx_dss_hdmi_dma_addrs, > .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs), > .user = OCP_USER_SDMA, > @@ -1544,7 +1544,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { > .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs), > .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, > .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs), > - .main_clk = "dss_fck", > + .main_clk = "dss_dss_clk", > .prcm = { > .omap4 = { > .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, > @@ -1595,7 +1595,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { > static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { > .master =&omap44xx_l3_main_2_hwmod, > .slave =&omap44xx_dss_rfbi_hwmod, > - .clk = "l3_div_ck", > + .clk = "dss_fck", > .addr = omap44xx_dss_rfbi_dma_addrs, > .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs), > .user = OCP_USER_SDMA, > @@ -1634,7 +1634,7 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { > .class =&omap44xx_rfbi_hwmod_class, > .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, > .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs), > - .main_clk = "dss_fck", > + .main_clk = "dss_dss_clk", > .prcm = { > .omap4 = { > .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, > @@ -1670,7 +1670,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { > static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { > .master =&omap44xx_l3_main_2_hwmod, > .slave =&omap44xx_dss_venc_hwmod, > - .clk = "l3_div_ck", > + .clk = "dss_fck", > .addr = omap44xx_dss_venc_dma_addrs, > .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs), > .user = OCP_USER_SDMA, > @@ -1707,7 +1707,7 @@ static struct omap_hwmod_opt_clk venc_opt_clks[] = { > static struct omap_hwmod omap44xx_dss_venc_hwmod = { > .name = "dss_venc", > .class =&omap44xx_venc_hwmod_class, > - .main_clk = "dss_fck", > + .main_clk = "dss_dss_clk", > .prcm = { > .omap4 = { > .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, > > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, 2011-06-07 at 13:37 +0200, Cousson, Benoit wrote: > On 6/7/2011 8:52 AM, Valkeinen, Tomi wrote: > > On Mon, 2011-06-06 at 17:28 +0200, Cousson, Benoit wrote: > > > >> Before doing that, could you maybe just try something to make OMAP4 > >> looks a little bit more like OMAP3? > >> > >> dss_fck -> ick > >> dss_dss_fck -> main_clk > >> > >> That should ensure that both modulemode and the PRCM fclk will be > >> managed by pm_runtime. > > > > I made the changes as you suggested, and while I haven't made the > > changes to omapdss yet to see if I can remove the dispc_runtime_get/put > > style function, I can boot up and start the dss. > > > > However, after booting up but before enabling the dss driver, I can see > > that the clock counts are: > > > > dss_tv_clk 0 > > dss_sys_clk 0 > > dss_fck 7 > > dss_dss_clk 0 > > dss_48mhz_clk 0 > > > > So the modulemode is set for all dss hwmods? Isn't this exactly how it's > > _not_ meant to be, as modulemode should be set only after enabling the > > fck? > > The issue is that there is only one modulemode for the whole DSS. > Potentially only the dss_hwmod should have it. But then you have to > ensure that this device is enabled before any other DSS devices. Does that change anything? Isn't the above (modulemode enabled before opt clock) still true, even if it was enabled only once for the dss_core hwmod? And for PM, it doesn't matter if the dss_fck is enabled once or seven times, I presume a use count of one will still prevent RET or OFF? > If you cannot do that at your level, we will have to set a hwmod > dependency between DSS modules and the main DSS subsystem. > For the moment we do not have such HW dependencies. I can do this in the driver, and in fact I already do. The dss_core hwmod is enabled by all the other hwmods before they do anything. My reasoning for this dependency is that the dss_core contains for example the clock mux registers, and other misc registers used by most other dss modules. But I'm not sure if this dependency should be in the hwmod level or not. Tomi -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 6/7/2011 1:51 PM, Valkeinen, Tomi wrote: > On Tue, 2011-06-07 at 13:37 +0200, Cousson, Benoit wrote: >> On 6/7/2011 8:52 AM, Valkeinen, Tomi wrote: >>> On Mon, 2011-06-06 at 17:28 +0200, Cousson, Benoit wrote: >>> >>>> Before doing that, could you maybe just try something to make OMAP4 >>>> looks a little bit more like OMAP3? >>>> >>>> dss_fck -> ick >>>> dss_dss_fck -> main_clk >>>> >>>> That should ensure that both modulemode and the PRCM fclk will be >>>> managed by pm_runtime. >>> >>> I made the changes as you suggested, and while I haven't made the >>> changes to omapdss yet to see if I can remove the dispc_runtime_get/put >>> style function, I can boot up and start the dss. >>> >>> However, after booting up but before enabling the dss driver, I can see >>> that the clock counts are: >>> >>> dss_tv_clk 0 >>> dss_sys_clk 0 >>> dss_fck 7 >>> dss_dss_clk 0 >>> dss_48mhz_clk 0 >>> >>> So the modulemode is set for all dss hwmods? Isn't this exactly how it's >>> _not_ meant to be, as modulemode should be set only after enabling the >>> fck? >> >> The issue is that there is only one modulemode for the whole DSS. >> Potentially only the dss_hwmod should have it. But then you have to >> ensure that this device is enabled before any other DSS devices. > > Does that change anything? Isn't the above (modulemode enabled before > opt clock) still true, even if it was enabled only once for the dss_core > hwmod? It does not really change anything, but it is more accurate. Modulemode need to be enable after the opt clocks that act as a functional clock and before enabling HW_AUTO for the clockdomain. The important parameter is the clock domain mode change. It is another issue that we have to fix. It might not affect you for the moment. > And for PM, it doesn't matter if the dss_fck is enabled once or seven > times, I presume a use count of one will still prevent RET or OFF? > >> If you cannot do that at your level, we will have to set a hwmod >> dependency between DSS modules and the main DSS subsystem. >> For the moment we do not have such HW dependencies. > > I can do this in the driver, and in fact I already do. The dss_core > hwmod is enabled by all the other hwmods before they do anything. > > My reasoning for this dependency is that the dss_core contains for > example the clock mux registers, and other misc registers used by most > other dss modules. But I'm not sure if this dependency should be in the > hwmod level or not. It makes sense for me as well to have that dependency between drivers. Having it for hwmod for my point of view will make the hwmod state out of sync with the driver that manage it potentially. That kind of hard coded dependencies at hwmod level should maybe be considered only if the dependent hwmod does not belong to any driver. Benoit -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, 2011-06-07 at 18:43 +0200, Cousson, Benoit wrote: > On 6/7/2011 1:51 PM, Valkeinen, Tomi wrote: > > On Tue, 2011-06-07 at 13:37 +0200, Cousson, Benoit wrote: > >> The issue is that there is only one modulemode for the whole DSS. > >> Potentially only the dss_hwmod should have it. But then you have to > >> ensure that this device is enabled before any other DSS devices. > > > > Does that change anything? Isn't the above (modulemode enabled before > > opt clock) still true, even if it was enabled only once for the dss_core > > hwmod? > > It does not really change anything, but it is more accurate. > Modulemode need to be enable after the opt clocks that act as a > functional clock and before enabling HW_AUTO for the clockdomain. > > The important parameter is the clock domain mode change. It is another > issue that we have to fix. It might not affect you for the moment. Ok. But the main issue now is the PM. If I change the clocks in hwmod data as you suggested, dss_fck will always stay enabled and prevent RET and OFF. So the fix is not acceptable even for temporary use. So is there some way to fix this, or shall we just go forward with the current patch series having the somewhat hacky way to use pm_runtime? I would personally like to get the driver right from the start, even if that means more hacks in the hwmod fmwk (because that's where the problems are). But if that is very difficult, I'm fine with the current patch series. Tomi -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index b374cd0..d7d86b6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1133,7 +1133,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_hwmod, - .clk = "l3_div_ck", + .clk = "dss_fck", .addr = omap44xx_dss_dma_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs), .user = OCP_USER_SDMA, @@ -1170,7 +1170,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = { static struct omap_hwmod omap44xx_dss_hwmod = { .name = "dss_core", .class = &omap44xx_dss_hwmod_class, - .main_clk = "dss_fck", + .main_clk = "dss_dss_clk", .prcm = { .omap4 = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, @@ -1230,7 +1230,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_dispc_hwmod, - .clk = "l3_div_ck", + .clk = "dss_fck", .addr = omap44xx_dss_dispc_dma_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs), .user = OCP_USER_SDMA, @@ -1279,7 +1279,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs), .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs), - .main_clk = "dss_fck", + .main_clk = "dss_dss_clk", .prcm = { .omap4 = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, @@ -1335,7 +1335,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_dsi1_hwmod, - .clk = "l3_div_ck", + .clk = "dss_fck", .addr = omap44xx_dss_dsi1_dma_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs), .user = OCP_USER_SDMA, @@ -1377,7 +1377,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs), .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs), - .main_clk = "dss_fck", + .main_clk = "dss_dss_clk", .prcm = { .omap4 = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, @@ -1412,7 +1412,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_dsi2_hwmod, - .clk = "l3_div_ck", + .clk = "dss_fck", .addr = omap44xx_dss_dsi2_dma_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs), .user = OCP_USER_SDMA, @@ -1449,7 +1449,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs), .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs), - .main_clk = "dss_fck", + .main_clk = "dss_dss_clk", .prcm = { .omap4 = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, @@ -1502,7 +1502,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "l3_div_ck", + .clk = "dss_fck", .addr = omap44xx_dss_hdmi_dma_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs), .user = OCP_USER_SDMA, @@ -1544,7 +1544,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs), .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs), - .main_clk = "dss_fck", + .main_clk = "dss_dss_clk", .prcm = { .omap4 = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, @@ -1595,7 +1595,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_rfbi_hwmod, - .clk = "l3_div_ck", + .clk = "dss_fck", .addr = omap44xx_dss_rfbi_dma_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs), .user = OCP_USER_SDMA, @@ -1634,7 +1634,7 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { .class = &omap44xx_rfbi_hwmod_class, .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs), - .main_clk = "dss_fck", + .main_clk = "dss_dss_clk", .prcm = { .omap4 = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, @@ -1670,7 +1670,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_venc_hwmod, - .clk = "l3_div_ck", + .clk = "dss_fck", .addr = omap44xx_dss_venc_dma_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs), .user = OCP_USER_SDMA, @@ -1707,7 +1707,7 @@ static struct omap_hwmod_opt_clk venc_opt_clks[] = { static struct omap_hwmod omap44xx_dss_venc_hwmod = { .name = "dss_venc", .class = &omap44xx_venc_hwmod_class, - .main_clk = "dss_fck", + .main_clk = "dss_dss_clk", .prcm = { .omap4 = { .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,