From patchwork Thu Jul 28 11:48:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 1015372 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6SBnI1a017295 for ; Thu, 28 Jul 2011 11:49:19 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754837Ab1G1LtS (ORCPT ); Thu, 28 Jul 2011 07:49:18 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:54330 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755528Ab1G1LtR convert rfc822-to-8bit (ORCPT ); Thu, 28 Jul 2011 07:49:17 -0400 Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6SBnGt0020183 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 28 Jul 2011 06:49:16 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep33.itg.ti.com (8.13.7/8.13.8) with ESMTP id p6SBnGNR021082 for ; Thu, 28 Jul 2011 06:49:16 -0500 (CDT) Received: from dnce72.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6SBnF2J015334 for ; Thu, 28 Jul 2011 06:49:16 -0500 (CDT) thread-index: AcxNHGBLMfm7JIulToazreoG1LE8QA== Content-Class: urn:content-classes:message Importance: normal X-MimeOLE: Produced By Microsoft MimeOLE V6.00.3790.4657 Received: from localhost.localdomain (172.24.88.3) by dnce72.ent.ti.com (137.167.131.87) with Microsoft SMTP Server (TLS) id 8.3.106.1; Thu, 28 Jul 2011 13:49:15 +0200 From: Tero Kristo To: Subject: [PATCHv4 4/4] TEMP: OMAP3: beagle rev-c4: enable OPP6 Date: Thu, 28 Jul 2011 14:48:59 +0300 Message-ID: <1311853739-18984-5-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1311853739-18984-1-git-send-email-t-kristo@ti.com> References: <1311853739-18984-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 28 Jul 2011 11:49:19 +0000 (UTC) Beagleboard rev-c4 has a speed sorted OMAP3530 chip which can run at 720MHz. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/board-omap3beagle.c | 32 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/opp3xxx_data.c | 4 +++ 2 files changed, 36 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 34f8411..ba84c0e 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -468,6 +468,38 @@ static void __init beagle_opp_init(void) return; } + /* Custom OPP enabled for C4 */ + if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4) { + struct omap_hwmod *mh = omap_hwmod_lookup("mpu"); + struct omap_hwmod *dh = omap_hwmod_lookup("iva"); + struct device *dev; + + if (!mh || !dh) { + pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n", + __func__, mh, dh); + } + /* Enable MPU 720MHz opp */ + dev = &mh->od->pdev.dev; + r = opp_enable(dev, 720000000); + + /* Enable IVA 520MHz opp */ + dev = &dh->od->pdev.dev; + r |= opp_enable(dev, 520000000); + + if (r) { + pr_err("%s: failed to enable higher opp %d\n", + __func__, r); + /* + * Cleanup - disable the higher freqs - we dont care + * about the results + */ + dev = &mh->od->pdev.dev; + opp_disable(dev, 720000000); + dev = &dh->od->pdev.dev; + opp_disable(dev, 520000000); + } + } + /* Custom OPP enabled for XM */ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { struct omap_hwmod *mh = omap_hwmod_lookup("mpu"); diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c index d95f3f9..a0f5fe1 100644 --- a/arch/arm/mach-omap2/opp3xxx_data.c +++ b/arch/arm/mach-omap2/opp3xxx_data.c @@ -98,6 +98,8 @@ static struct omap_opp_def __initdata omap34xx_opp_def_list[] = { OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV), /* MPU OPP5 */ OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV), + /* MPU OPP6 : omap3530 high speed grade only */ + OPP_INITIALIZER("mpu", false, 720000000, OMAP3430_VDD_MPU_OPP5_UV), /* * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is @@ -123,6 +125,8 @@ static struct omap_opp_def __initdata omap34xx_opp_def_list[] = { OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV), /* DSP OPP5 */ OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV), + /* DSP OPP6 : omap3530 high speed grade only */ + OPP_INITIALIZER("iva", false, 520000000, OMAP3430_VDD_MPU_OPP5_UV), }; static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {