From patchwork Mon Aug 8 09:15:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1043522 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p789FYZc009522 for ; Mon, 8 Aug 2011 09:15:38 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752376Ab1HHJPc (ORCPT ); Mon, 8 Aug 2011 05:15:32 -0400 Received: from na3sys009aog121.obsmtp.com ([74.125.149.145]:55589 "EHLO na3sys009aog121.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752346Ab1HHJPc (ORCPT ); Mon, 8 Aug 2011 05:15:32 -0400 Received: from mail-fx0-f46.google.com ([209.85.161.46]) (using TLSv1) by na3sys009aob121.postini.com ([74.125.148.12]) with SMTP ID DSNKTj+pMsAXDGygT2fUksQdpb/hQFCW2weu@postini.com; Mon, 08 Aug 2011 02:15:31 PDT Received: by mail-fx0-f46.google.com with SMTP id 19so7517913fxh.33 for ; Mon, 08 Aug 2011 02:15:30 -0700 (PDT) Received: by 10.204.97.204 with SMTP id m12mr1516152bkn.381.1312794930604; Mon, 08 Aug 2011 02:15:30 -0700 (PDT) Received: from localhost.localdomain (a62-248-128-208.elisa-laajakaista.fi [62.248.128.208]) by mx.google.com with ESMTPS id b3sm1571974bke.11.2011.08.08.02.15.28 (version=SSLv3 cipher=OTHER); Mon, 08 Aug 2011 02:15:29 -0700 (PDT) From: Tomi Valkeinen To: paul@pwsan.com, linux-omap@vger.kernel.org, b-cousson@ti.com Cc: archit@ti.com, Tomi Valkeinen Subject: [PATCHv2 3/5] OMAP4: HWMOD: fix DSS opt clocks Date: Mon, 8 Aug 2011 12:15:12 +0300 Message-Id: <1312794914-22894-4-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1312794914-22894-1-git-send-email-tomi.valkeinen@ti.com> References: <1312794914-22894-1-git-send-email-tomi.valkeinen@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 08 Aug 2011 09:15:39 +0000 (UTC) Remove the extra dss_dss_clk from dss_core's opt-clocks. dss_dss_clk is the fck, and thus not an opt-clock. Add HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core so that dss_core's reset can finish. Remove the opt clocks for dispc, as they are not needed. Change the main_clk for hdmi and venc to dss_48mhz_clk and dss_tv_clk, respectively. Cc: Benoit Cousson Signed-off-by: Tomi Valkeinen Acked-by: Benoit Cousson --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 16 ++++------------ 1 files changed, 4 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 6201422..8b74058 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1257,12 +1257,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { static struct omap_hwmod_opt_clk dss_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, { .role = "tv_clk", .clk = "dss_tv_clk" }, - { .role = "dss_clk", .clk = "dss_dss_clk" }, - { .role = "video_clk", .clk = "dss_48mhz_clk" }, + { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, }; static struct omap_hwmod omap44xx_dss_hwmod = { .name = "dss_core", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .class = &omap44xx_dss_hwmod_class, .clkdm_name = "l3_dss_clkdm", .main_clk = "dss_dss_clk", @@ -1358,12 +1358,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { &omap44xx_l4_per__dss_dispc, }; -static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = { - { .role = "sys_clk", .clk = "dss_sys_clk" }, - { .role = "tv_clk", .clk = "dss_tv_clk" }, - { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, -}; - static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap44xx_dispc_hwmod_class, @@ -1377,8 +1371,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, }, - .opt_clks = dss_dispc_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks), .slaves = omap44xx_dss_dispc_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -1645,7 +1637,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { .clkdm_name = "l3_dss_clkdm", .mpu_irqs = omap44xx_dss_hdmi_irqs, .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, - .main_clk = "dss_dss_clk", + .main_clk = "dss_48mhz_clk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, @@ -1808,7 +1800,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { .name = "dss_venc", .class = &omap44xx_venc_hwmod_class, .clkdm_name = "l3_dss_clkdm", - .main_clk = "dss_dss_clk", + .main_clk = "dss_tv_clk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,