From patchwork Thu Sep 8 13:36:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "K, Mythri P" X-Patchwork-Id: 1129902 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p88Digle003719 for ; Thu, 8 Sep 2011 13:44:43 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932928Ab1IHNoi (ORCPT ); Thu, 8 Sep 2011 09:44:38 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:59431 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932874Ab1IHNog (ORCPT ); Thu, 8 Sep 2011 09:44:36 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p88DiWPO023852 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 8 Sep 2011 08:44:35 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p88DiVeC003387 for ; Thu, 8 Sep 2011 19:14:31 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Thu, 8 Sep 2011 19:14:31 +0530 Received: from localhost.localdomain (graphicspc.apr.dhcp.ti.com [172.24.136.217]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p88DiTJ5027781; Thu, 8 Sep 2011 19:14:31 +0530 (IST) From: To: , CC: Mythri P K Subject: [PATCH 02/10] OMAP4: DSS: HDMI: Move pll and video configuration Date: Thu, 8 Sep 2011 19:06:19 +0530 Message-ID: <1315488987-4546-3-git-send-email-mythripk@ti.com> X-Mailer: git-send-email 1.5.6.3 In-Reply-To: <1315488987-4546-2-git-send-email-mythripk@ti.com> References: <1315488987-4546-1-git-send-email-mythripk@ti.com> <1315488987-4546-2-git-send-email-mythripk@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 08 Sep 2011 13:44:43 +0000 (UTC) From: Mythri P K As the pll and the video configuration info are part of the ip_data, pll and video structures are moved to the ip_data structure. Also the pll and video configuration functions are modified accordingly to take care of the structure movement. Signed-off-by: Mythri P K --- drivers/video/omap2/dss/dss.h | 8 +++++++ drivers/video/omap2/dss/hdmi.c | 42 ++++++++++++++++++--------------------- drivers/video/omap2/dss/hdmi.h | 25 +++++++++-------------- 3 files changed, 37 insertions(+), 38 deletions(-) diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index a095a62..4cb264e 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -150,6 +150,13 @@ struct dsi_clock_info { bool use_sys_clk; }; +enum hdmi_clk_refsel { + HDMI_REFSEL_PCLK = 0, + HDMI_REFSEL_REF1 = 1, + HDMI_REFSEL_REF2 = 2, + HDMI_REFSEL_SYSCLK = 3 +}; + /* HDMI PLL structure */ struct hdmi_pll_info { u16 regn; @@ -158,6 +165,7 @@ struct hdmi_pll_info { u16 regm2; u16 regsd; u16 dcofreq; + enum hdmi_clk_refsel refsel; }; struct seq_file; diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index bfd113c..47e9f4a 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -59,7 +59,6 @@ static struct { u8 edid[HDMI_EDID_MAX_LENGTH]; u8 edid_set; bool custom_set; - struct hdmi_config cfg; struct clk *sys_clk; } hdmi; @@ -229,12 +228,11 @@ int hdmi_init_display(struct omap_dss_device *dssdev) return 0; } -static int hdmi_pll_init(struct hdmi_ip_data *ip_data, - enum hdmi_clk_refsel refsel, int dcofreq, - struct hdmi_pll_info *fmt, u16 sd) +static int hdmi_pll_init(struct hdmi_ip_data *ip_data) { u32 r; void __iomem *pll_base = hdmi_pll_base(ip_data); + struct hdmi_pll_info *fmt = &ip_data->pll_data; /* PLL start always use manual mode */ REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); @@ -250,10 +248,11 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data, r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ + r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */ - if (dcofreq) { + if (fmt->dcofreq) { /* divider programming for frequency beyond 1000Mhz */ - REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10); + REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ } else { r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ @@ -379,11 +378,9 @@ static int hdmi_phy_init(struct hdmi_ip_data *ip_data) return 0; } -static int hdmi_pll_program(struct hdmi_ip_data *ip_data, - struct hdmi_pll_info *fmt) +static int hdmi_pll_program(struct hdmi_ip_data *ip_data) { u16 r = 0; - enum hdmi_clk_refsel refsel; r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); if (r) @@ -397,9 +394,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data, if (r) return r; - refsel = HDMI_REFSEL_SYSCLK; - - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd); + r = hdmi_pll_init(ip_data); if (r) return r; @@ -1015,8 +1010,7 @@ static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data, hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); } -static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, - struct hdmi_config *cfg) +static void hdmi_basic_configure(struct hdmi_ip_data *ip_data) { /* HDMI */ struct omap_video_timings video_timing; @@ -1026,6 +1020,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, struct hdmi_core_infoframe_avi avi_cfg; struct hdmi_core_video_config v_core_cfg; struct hdmi_core_packet_enable_repeat repeat_cfg; + struct hdmi_config *cfg = &ip_data->cfg; hdmi_wp_init(&video_timing, &video_format, &video_interface); @@ -1034,8 +1029,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, &avi_cfg, &repeat_cfg); - hdmi_wp_video_init_format(&video_format, - &video_timing, cfg); + hdmi_wp_video_init_format(&video_format, &video_timing, cfg); hdmi_wp_video_config_timing(ip_data, &video_timing); @@ -1154,6 +1148,9 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, pi->dcofreq = phy > 1000 * 100; pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10; + /* Set the reference clock to sysclk reference */ + pi->refsel = HDMI_REFSEL_SYSCLK; + DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); } @@ -1161,7 +1158,6 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, static int hdmi_power_on(struct omap_dss_device *dssdev) { int r, code = 0; - struct hdmi_pll_info pll_data; struct omap_video_timings *p; unsigned long phy; @@ -1183,16 +1179,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) } code = get_timings_index(); dssdev->panel.timings = cea_vesa_timings[code].timings; - update_hdmi_timings(&hdmi.cfg, p, code); + update_hdmi_timings(&hdmi.ip_data.cfg, p, code); phy = p->pixel_clock; - hdmi_compute_pll(dssdev, phy, &pll_data); + hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); hdmi_wp_video_start(&hdmi.ip_data, 0); /* config the PLL and PHY hdmi_set_pll_pwrfirst */ - r = hdmi_pll_program(&hdmi.ip_data, &pll_data); + r = hdmi_pll_program(&hdmi.ip_data); if (r) { DSSDBG("Failed to lock PLL\n"); goto err; @@ -1204,9 +1200,9 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) goto err; } - hdmi.cfg.cm.mode = hdmi.mode; - hdmi.cfg.cm.code = hdmi.code; - hdmi_basic_configure(&hdmi.ip_data, &hdmi.cfg); + hdmi.ip_data.cfg.cm.mode = hdmi.mode; + hdmi.ip_data.cfg.cm.code = hdmi.code; + hdmi_basic_configure(&hdmi.ip_data); /* Make selection of HDMI in DSS */ dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index ee37bd9..d2913f8 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h @@ -218,13 +218,6 @@ enum hdmi_pll_pwr { HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 }; -enum hdmi_clk_refsel { - HDMI_REFSEL_PCLK = 0, - HDMI_REFSEL_REF1 = 1, - HDMI_REFSEL_REF2 = 2, - HDMI_REFSEL_SYSCLK = 3 -}; - enum hdmi_core_inputbus_width { HDMI_INPUT_8BIT = 0, HDMI_INPUT_10BIT = 1, @@ -558,14 +551,6 @@ struct hdmi_video_interface { int tm; /* Timing mode */ }; -struct hdmi_ip_data { - void __iomem *base_wp; /* HDMI wrapper */ - unsigned long core_sys_offset; - unsigned long core_av_offset; - unsigned long pll_offset; - unsigned long phy_offset; -}; - struct hdmi_cm { int code; int mode; @@ -577,6 +562,16 @@ struct hdmi_config { struct hdmi_cm cm; }; +struct hdmi_ip_data { + void __iomem *base_wp; /* HDMI wrapper */ + unsigned long core_sys_offset; + unsigned long core_av_offset; + unsigned long pll_offset; + unsigned long phy_offset; + struct hdmi_config cfg; + struct hdmi_pll_info pll_data; +}; + struct hdmi_audio_format { enum hdmi_stereo_channels stereo_channels; u8 active_chnnls_msk;