From patchwork Fri Jun 29 09:11:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruslan Bilovol X-Patchwork-Id: 1130991 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id E0EA6DFF34 for ; Fri, 29 Jun 2012 09:11:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753311Ab2F2JLJ (ORCPT ); Fri, 29 Jun 2012 05:11:09 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:57483 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752273Ab2F2JLI (ORCPT ); Fri, 29 Jun 2012 05:11:08 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q5T9B6hM018166; Fri, 29 Jun 2012 04:11:06 -0500 Received: from DFLE70.ent.ti.com (dfle70.ent.ti.com [128.247.5.40]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q5T9B6xB022320; Fri, 29 Jun 2012 04:11:06 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle70.ent.ti.com (128.247.5.40) with Microsoft SMTP Server id 14.1.323.3; Fri, 29 Jun 2012 04:11:06 -0500 Received: from localhost (uglx0155540.ucm2.emeaucm.ext.ti.com [10.167.145.75]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q5T9B50C032063; Fri, 29 Jun 2012 04:11:06 -0500 From: Ruslan Bilovol To: , CC: , Subject: [PATCH 1/2] omap4: control: Add the CONTROL_SMART2IO_PADCONF_2 register definition Date: Fri, 29 Jun 2012 12:11:04 +0300 Message-ID: <1340961065-26938-1-git-send-email-ruslan.bilovol@ti.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org This patch adds missing CONTROL_SMART2IO_PADCONF_2 register definition Signed-off-by: Ruslan Bilovol --- .../include/mach/ctrl_module_pad_core_44xx.h | 45 ++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h index c88420d..d512ade 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h @@ -46,6 +46,7 @@ #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2 0x05cc #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 @@ -764,6 +765,50 @@ #define OMAP4_HSI_DR0_LB_SHIFT 10 #define OMAP4_HSI_DR0_LB_MASK (1 << 10) +/* CONTROL_SMART2IO_PADCONF_2 */ +#define OMAP4_DPM_DR1_DS_SHIFT 31 +#define OMAP4_DPM_DR1_DS_MASK (1 << 31) +#define OMAP4_DPM_DR2_DS_SHIFT 30 +#define OMAP4_DPM_DR2_DS_MASK (1 << 30) +#define OMAP4_DPM_DR3_DS_SHIFT 29 +#define OMAP4_DPM_DR3_DS_MASK (1 << 29) +#define OMAP4_GPIO_DR10_DS_SHIFT 28 +#define OMAP4_GPIO_DR10_DS_MASK (1 << 28) +#define OMAP4_HSI2_DR0_DS_SHIFT 27 +#define OMAP4_HSI2_DR0_DS_MASK (1 << 27) +#define OMAP4_HSI2_DR1_DS_SHIFT 26 +#define OMAP4_HSI2_DR1_DS_MASK (1 << 26) +#define OMAP4_HSI2_DR2_DS_SHIFT 25 +#define OMAP4_HSI2_DR2_DS_MASK (1 << 25) +#define OMAP4_SDMMC3_DR0_DS_SHIFT 24 +#define OMAP4_SDMMC3_DR0_DS_MASK (1 << 24) +#define OMAP4_SDMMC4_DR0_DS_SHIFT 23 +#define OMAP4_SDMMC4_DR0_DS_MASK (1 << 23) +#define OMAP4_SDMMC4_DR1_DS_SHIFT 22 +#define OMAP4_SDMMC4_DR1_DS_MASK (1 << 22) +#define OMAP4_SPI3_DR0_DS_SHIFT 21 +#define OMAP4_SPI3_DR0_DS_MASK (1 << 21) +#define OMAP4_SPI3_DR1_DS_SHIFT 20 +#define OMAP4_SPI3_DR1_DS_MASK (1 << 20) +#define OMAP4_UART3_DR2_DS_SHIFT 19 +#define OMAP4_UART3_DR2_DS_MASK (1 << 19) +#define OMAP4_UART3_DR3_DS_SHIFT 18 +#define OMAP4_UART3_DR3_DS_MASK (1 << 18) +#define OMAP4_UART3_DR4_DS_SHIFT 17 +#define OMAP4_UART3_DR4_DS_MASK (1 << 17) +#define OMAP4_UART3_DR5_DS_SHIFT 16 +#define OMAP4_UART3_DR5_DS_MASK (1 << 16) +#define OMAP4_USBA0_DR0_DS_SHIFT 15 +#define OMAP4_USBA0_DR0_DS_MASK (1 << 15) +#define OMAP4_USBA0_DR1_DS_SHIFT 14 +#define OMAP4_USBA0_DR1_DS_MASK (1 << 14) +#define OMAP4_USBA_DR2_DS_SHIFT 13 +#define OMAP4_USBA_DR2_DS_MASK (1 << 13) +#define OMAP4_USBB2_DR0_DS_SHIFT 12 +#define OMAP4_USBB2_DR0_DS_MASK (1 << 12) +#define OMAP4_USBB1_DR0_DS_SHIFT 11 +#define OMAP4_USBB1_DR0_DS_MASK (1 << 11) + /* CONTROL_USBB_HSIC */ #define OMAP4_USBB2_DR1_SR_SHIFT 30 #define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)