From patchwork Thu Jul 5 12:08:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 1159721 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 8059EDFB7C for ; Thu, 5 Jul 2012 12:10:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752630Ab2GEMKM (ORCPT ); Thu, 5 Jul 2012 08:10:12 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:40987 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752184Ab2GEMKL (ORCPT ); Thu, 5 Jul 2012 08:10:11 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q65C9I6k016959; Thu, 5 Jul 2012 07:09:19 -0500 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q65C9ILO010787; Thu, 5 Jul 2012 17:39:18 +0530 (IST) Received: from dbdp33.itg.ti.com (172.24.170.252) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Thu, 5 Jul 2012 17:39:18 +0530 Received: from ula0393909.apr.dhcp.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp33.itg.ti.com (8.13.8/8.13.8) with ESMTP id q65C94CV020675; Thu, 5 Jul 2012 17:39:17 +0530 From: Santosh Shilimkar To: CC: , , R Sricharan , Santosh Shilimkar Subject: [PATCH v1 07/14] ARM: OMAP5: l3: Add l3 error handler support for omap5. Date: Thu, 5 Jul 2012 17:38:49 +0530 Message-ID: <1341490136-25901-12-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1341490136-25901-1-git-send-email-santosh.shilimkar@ti.com> References: <1341490136-25901-1-git-send-email-santosh.shilimkar@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: R Sricharan The l3 interconnect ip is same for OMAP4 and OMAP5. So reuse the l3 error handler error code for OMAP5 as well. Also a few targets has been newly added for OMAP5. So updating the driver for that here. Signed-off-by: R Sricharan Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/devices.c | 2 +- arch/arm/mach-omap2/omap_l3_noc.h | 22 ++++++++++++++++++---- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index bb6b364..365421d 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -191,6 +191,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o # L3 interconnect obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o +obj-$(CONFIG_SOC_OMAP5) += omap_l3_noc.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 7b4b932..f443f24 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -84,7 +84,7 @@ static int __init omap4_l3_init(void) * To avoid code running on other OMAPs in * multi-omap builds */ - if (!(cpu_is_omap44xx())) + if (!cpu_is_omap44xx() && !cpu_is_omap54xx()) return -ENODEV; for (i = 0; i < L3_MODULES; i++) { diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h index 90b5098..a6ce34d 100644 --- a/arch/arm/mach-omap2/omap_l3_noc.h +++ b/arch/arm/mach-omap2/omap_l3_noc.h @@ -51,7 +51,9 @@ static u32 l3_targ_inst_clk1[] = { 0x200, /* DMM2 */ 0x300, /* ABE */ 0x400, /* L4CFG */ - 0x600 /* CLK2 PWR DISC */ + 0x600, /* CLK2 PWR DISC */ + 0x0, /* Host CLK1 */ + 0x900 /* L4 Wakeup */ }; static u32 l3_targ_inst_clk2[] = { @@ -72,11 +74,16 @@ static u32 l3_targ_inst_clk2[] = { 0xE00, /* missing in TRM corresponds to AES2*/ 0xC00, /* L4 PER3 */ 0xA00, /* L4 PER1*/ - 0xB00 /* L4 PER2*/ + 0xB00, /* L4 PER2*/ + 0x0, /* HOST CLK2 */ + 0x1800, /* CAL */ + 0x1700 /* LLI */ }; static u32 l3_targ_inst_clk3[] = { - 0x0100 /* EMUSS */ + 0x0100 /* EMUSS */, + 0x0300, /* DEBUGSS_CT_TBR */ + 0x0 /* HOST CLK3 */ }; static struct l3_masters_data { @@ -110,13 +117,15 @@ static struct l3_masters_data { { 0xC8, "USBHOSTFS"} }; -static char *l3_targ_inst_name[L3_MODULES][18] = { +static char *l3_targ_inst_name[L3_MODULES][21] = { { "DMM1", "DMM2", "ABE", "L4CFG", "CLK2 PWR DISC", + "HOST CLK1", + "L4 WAKEUP" }, { "CORTEX M3" , @@ -137,9 +146,14 @@ static char *l3_targ_inst_name[L3_MODULES][18] = { "L4 PER3", "L4 PER1", "L4 PER2", + "HOST CLK2", + "CAL", + "LLI" }, { "EMUSS", + "DEBUG SOURCE", + "HOST CLK3" }, };