From patchwork Thu Jul 5 12:08:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 1159771 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id EE86E3FD4F for ; Thu, 5 Jul 2012 12:10:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753836Ab2GEMKl (ORCPT ); Thu, 5 Jul 2012 08:10:41 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:56040 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753630Ab2GEMKi (ORCPT ); Thu, 5 Jul 2012 08:10:38 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id q65C9DnO027075; Thu, 5 Jul 2012 07:09:14 -0500 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q65C9CBx010740; Thu, 5 Jul 2012 17:39:12 +0530 (IST) Received: from dbdp33.itg.ti.com (172.24.170.252) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Thu, 5 Jul 2012 17:39:12 +0530 Received: from ula0393909.apr.dhcp.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp33.itg.ti.com (8.13.8/8.13.8) with ESMTP id q65C94CN020675; Thu, 5 Jul 2012 17:39:12 +0530 From: Santosh Shilimkar To: CC: , , R Sricharan , Santosh Shilimkar Subject: [PATCH v1 02/14] ARM: OMAP: counter-32k: Select the CR register offset using the IP scheme. Date: Thu, 5 Jul 2012 17:38:41 +0530 Message-ID: <1341490136-25901-4-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1341490136-25901-1-git-send-email-santosh.shilimkar@ti.com> References: <1341490136-25901-1-git-send-email-santosh.shilimkar@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: R Sricharan OMAP socs has a legacy and a highlander version of the 32k sync counter IP. The register offsets vary between the highlander and the legacy scheme. So use the 'SCHEME' bits(30-31) of the revision register to distinguish between the two versions and choose the CR register offset accordingly. Signed-off-by: R Sricharan Signed-off-by: Santosh Shilimkar --- arch/arm/plat-omap/counter_32k.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index 2132c4f..dbf1e03 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c @@ -29,7 +29,10 @@ #include /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ -#define OMAP2_32KSYNCNT_CR_OFF 0x10 +#define OMAP2_32KSYNCNT_REV_OFF 0x0 +#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) +#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 +#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 /* * 32KHz clocksource ... always available, on pretty most chips except @@ -84,9 +87,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase) int ret; /* - * 32k sync Counter register offset is at 0x10 + * 32k sync Counter IP register offsets vary between the + * highlander version and the legacy ones. + * The 'SCHEME' bits(30-31) of the revision register is used + * to identify the version. */ - sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF; + if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) & + OMAP2_32KSYNCNT_REV_SCHEME) + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; + else + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW; /* * 120000 rough estimate from the calculations in