From patchwork Thu Sep 13 10:20:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 1451191 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id B4825DF28C for ; Thu, 13 Sep 2012 10:21:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757305Ab2IMKVR (ORCPT ); Thu, 13 Sep 2012 06:21:17 -0400 Received: from service87.mimecast.com ([91.220.42.44]:48008 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757156Ab2IMKVM (ORCPT ); Thu, 13 Sep 2012 06:21:12 -0400 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 13 Sep 2012 11:21:11 +0100 Received: from e102568-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Thu, 13 Sep 2012 11:21:08 +0100 From: Lorenzo Pieralisi To: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org, Santosh Shilimkar , Lorenzo Pieralisi , Catalin Marinas , Will Deacon , Russell King , Nicolas Pitre , Colin Cross , Daniel Lezcano , Amit Kucheria , Dave Martin , Wenzeng Chen Subject: [RFC PATCH 6/6] ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API Date: Thu, 13 Sep 2012 11:20:51 +0100 Message-Id: <1347531651-28218-7-git-send-email-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com> References: <1347531651-28218-1-git-send-email-lorenzo.pieralisi@arm.com> X-OriginalArrivalTime: 13 Sep 2012 10:21:08.0034 (UTC) FILETIME=[7D363220:01CD9199] X-MC-Unique: 112091311211104901 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Santosh Shilimkar The ARMv7 processor setup function __v7_setup() cleans and invalidates the CPU cache before enabling MMU to start the CPU with a clean CPU local cache. But on ARMv7 architectures like Cortex-[A15/A8], this code will end up flushing the L2 caches(up to level of Coherency) which is undesirable and expensive. The setup functions are used in the CPU hotplug scenario too and hence flushing all cache levels should be avoided. This patch replaces the cache flushing call with the newly introduced v7 dcache LoUIS API where only cache levels up to LoUIS are cleaned and invalidated when a processors executes __v7_setup which is the expected behavior. For processors like A9 and A5 where the L2 cache is an outer one the behavior should be unchanged. Signed-off-by: Santosh Shilimkar Signed-off-by: Lorenzo Pieralisi --- arch/arm/mm/proc-v7.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c2e2b66..846d279 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -172,7 +172,7 @@ __v7_ca15mp_setup: __v7_setup: adr r12, __v7_setup_stack @ the local stack stmia r12, {r0-r5, r7, r9, r11, lr} - bl v7_flush_dcache_all + bl v7_flush_dcache_louis ldmia r12, {r0-r5, r7, r9, r11, lr} mrc p15, 0, r0, c0, c0, 0 @ read main ID register