From patchwork Thu Oct 4 11:57:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 1546141 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 57BBE3FC1A for ; Thu, 4 Oct 2012 11:56:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755565Ab2JDL4b (ORCPT ); Thu, 4 Oct 2012 07:56:31 -0400 Received: from na3sys009aog126.obsmtp.com ([74.125.149.155]:35613 "EHLO na3sys009aog126.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755560Ab2JDL4a (ORCPT ); Thu, 4 Oct 2012 07:56:30 -0400 Received: from mail-oa0-f46.google.com ([209.85.219.46]) (using TLSv1) by na3sys009aob126.postini.com ([74.125.148.12]) with SMTP ID DSNKUG15btm8r0gLUeva54dXuKSQmIX2HtYT@postini.com; Thu, 04 Oct 2012 04:56:30 PDT Received: by mail-oa0-f46.google.com with SMTP id h16so339707oag.19 for ; Thu, 04 Oct 2012 04:56:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=qGjrfIo8SXGaWeWuWG3dleDjmoFBwbK4+4g/TiZgbNs=; b=VcUQ8hUcxROwbzsxQbnGVJeM0iiX14cHgS2UUrNSqEb+qXRs/0+MEMmqBXSS6o1Tg6 l1X3EDVuWnjCxlWZFT1T5fJAxPhFx8HUYEROsfnKGbjB0MLwYWmBevgEhxbGrbylRO95 6M3Mq5toz7krXMEhoE8u669CGSiZJxtJVUZTcl/Lk7VY6wAOOcwGbWndcFLp2gkhN+JU tnxpeSP76g09NXBtfmbzueE28aehFdQF34RaDBlVobPYZlq3YPrOy88YgufBlKmbXk7L w0wFaNGsqG+36qA8BQiOTef1S0NnqzTiTZ+VxCR7jqOwovQWjv0AHWVY7S6ZUo0wLht2 jEQA== Received: by 10.60.4.67 with SMTP id i3mr4145343oei.38.1349351789786; Thu, 04 Oct 2012 04:56:29 -0700 (PDT) Received: from barack.emea.dhcp.ti.com (dragon.ti.com. [192.94.94.33]) by mx.google.com with ESMTPS id d6sm6435685obx.15.2012.10.04.04.56.27 (version=SSLv3 cipher=OTHER); Thu, 04 Oct 2012 04:56:29 -0700 (PDT) From: Peter Ujfalusi To: Tony Lindgren Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree-discuss@lists.ozlabs.org Subject: [PATCH 6/9] ARM/dts: omap4-sdp: pinmux configuration for audio Date: Thu, 4 Oct 2012 14:57:25 +0300 Message-Id: <1349351848-12972-7-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 1.7.12 In-Reply-To: <1349351848-12972-1-git-send-email-peter.ujfalusi@ti.com> References: <1349351848-12972-1-git-send-email-peter.ujfalusi@ti.com> X-Gm-Message-State: ALoCoQmXIaV8BHbV5EqyMTIBQ68d+oSEquMYU60bvspgHsjLMIa+LAdV7VLgbqQ2vYEVg+YW6uUK Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org u-boot stopped configuring 'non essential' pins recently. The kernel needs to configure the mux for audio needs. Since the pinmux for these IPs are static let pinctrl to handle the mux configuration for. Configuring the mux for: twl6040 (audpwron, irq), McPDM, DMIC, McBSP1 and McBSP2. Signed-off-by: Peter Ujfalusi --- arch/arm/boot/dts/omap4-sdp.dts | 53 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index cf09875..5b7e04f 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -117,6 +117,15 @@ }; &omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6040_pins + &mcpdm_pins + &dmic_pins + &mcbsp1_pins + &mcbsp2_pins + >; + uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */ @@ -141,6 +150,50 @@ 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */ >; }; + + twl6040_pins: pinmux_twl6040_pins { + pinctrl-single,pins = < + 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ + 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */ + >; + }; + + mcpdm_pins: pinmux_mcpdm_pins { + pinctrl-single,pins = < + 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */ + 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */ + 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */ + 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */ + 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ + >; + }; + + dmic_pins: pinmux_dmic_pins { + pinctrl-single,pins = < + 0xd0 0 /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */ + 0xd2 0x100 /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */ + 0xd4 0x100 /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */ + 0xd6 0x100 /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */ + >; + }; + + mcbsp1_pins: pinmux_mcbsp1_pins { + pinctrl-single,pins = < + 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */ + 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */ + 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */ + 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ + >; + }; + + mcbsp2_pins: pinmux_mcbsp2_pins { + pinctrl-single,pins = < + 0xb6 0x100 /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */ + 0xb8 0x108 /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */ + 0xba 0x8 /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */ + 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */ + >; + }; }; &i2c1 {