From patchwork Thu Oct 18 16:38:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 1612111 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id A07C43FE36 for ; Thu, 18 Oct 2012 16:38:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756968Ab2JRQiu (ORCPT ); Thu, 18 Oct 2012 12:38:50 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39898 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756693Ab2JRQiu (ORCPT ); Thu, 18 Oct 2012 12:38:50 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q9IGck1C023850; Thu, 18 Oct 2012 11:38:46 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9IGck4Y012421; Thu, 18 Oct 2012 11:38:46 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Thu, 18 Oct 2012 11:38:46 -0500 Received: from localhost (uglx0174654.ucm2.emeaucm.ext.ti.com [10.167.145.249]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9IGcjLX016921; Thu, 18 Oct 2012 11:38:45 -0500 From: Grygorii Strashko To: Paul Walmsley CC: Mike Turquette , Kevin Hilman , Tony Lindgren , , , Grygorii Strashko Subject: [RFC PATCH 2/2] ARM: OMAP4: clock: use omap4_clks_register API Date: Thu, 18 Oct 2012 19:38:17 +0300 Message-ID: <1350578297-22572-3-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1350578297-22572-1-git-send-email-grygorii.strashko@ti.com> References: <1350578297-22572-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Remove OMAP443x and OMAP446x specific clocks from omap44xx_clks array and add corresponding set of clocks per each SoC: - struct omap_clk omap44xx_clks[]; - common clocks set for all OMAP4 - struct omap_clk omap443x_clks[]; - specific clocks set for OMAP443x - struct omap_clk omap446x_clks[]; - specific clocks set for OMAP446x and don't rely on platform specific flags any more. Use omap4_clks_register() API to register and init OMAP4 set of clocks. With this change, we can now safely remove CK_443X/CK_446X etc macro usage. It has not been done in this patch, but if the approach is OK, then, it is possible to do the same. One additional benefit seen is that the match logic can entirely be skipped. Signed-off-by: Grygorii Strashko --- arch/arm/mach-omap2/clock44xx_data.c | 40 ++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 6efc30c..4060c9c 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3145,10 +3145,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), CLK(NULL, "aess_fck", &aess_fck, CK_443X), - CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), - CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), - CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), @@ -3346,19 +3343,27 @@ static struct omap_clk omap44xx_clks[] = { CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), + CLK(NULL, NULL, NULL, CK_443X), +}; + +static struct omap_clk omap443x_clks[] = { + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), + CLK(NULL, NULL, NULL, CK_443X), +}; + + +static struct omap_clk omap446x_clks[] = { + CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), + CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), + CLK(NULL, NULL, NULL, CK_446X), }; int __init omap4xxx_clk_init(void) { - struct omap_clk *c; - u32 cpu_clkflg; - if (cpu_is_omap443x()) { cpu_mask = RATE_IN_4430; - cpu_clkflg = CK_443X; } else if (cpu_is_omap446x() || cpu_is_omap447x()) { cpu_mask = RATE_IN_4460 | RATE_IN_4430; - cpu_clkflg = CK_446X | CK_443X; if (cpu_is_omap447x()) pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); @@ -3375,17 +3380,14 @@ int __init omap4xxx_clk_init(void) * omap2_clk_disable_clkdm_control(); */ - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); - c++) - clk_preinit(c->lk.clk); - - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); - c++) - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - omap2_init_clk_clkdm(c->lk.clk); - } + omap2_clks_register(omap44xx_clks); + + if (cpu_is_omap443x()) + omap2_clks_register(omap443x_clks); + else if (cpu_is_omap446x() || cpu_is_omap447x()) + omap2_clks_register(omap446x_clks); + else + return 0; /* Disable autoidle on all clocks; let the PM code enable it later */ omap_clk_disable_autoidle_all();