From patchwork Thu Nov 8 07:53:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: avinash philip X-Patchwork-Id: 1714301 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 0828A3FCDE for ; Thu, 8 Nov 2012 08:00:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752632Ab2KHH72 (ORCPT ); Thu, 8 Nov 2012 02:59:28 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:40247 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753030Ab2KHH71 (ORCPT ); Thu, 8 Nov 2012 02:59:27 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id qA87x6Lk009606; Thu, 8 Nov 2012 01:59:07 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA87x6R6017930; Thu, 8 Nov 2012 13:29:06 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Thu, 8 Nov 2012 13:29:06 +0530 Received: from localhost.localdomain (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA87saff015193; Thu, 8 Nov 2012 13:29:05 +0530 From: "Philip, Avinash" To: , , , , CC: , , , , , , , , , , "Philip, Avinash" , Rob Herring , Rob Landley Subject: [PATCH v2 08/10] pwm: pwm-tiehrpwm: Adding TBCLK gating support. Date: Thu, 8 Nov 2012 13:23:15 +0530 Message-ID: <1352361197-27442-9-git-send-email-avinashphilip@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1352361197-27442-1-git-send-email-avinashphilip@ti.com> References: <1352361197-27442-1-git-send-email-avinashphilip@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Some platforms (like AM33XX) requires clock gating from control module explicitly for TBCLK. Enabling of this clock required for the functioning of the time base sub module in EHRPWM module. So adding optional TBCLK handling if DT node populated with tbclkgating. This helps the driver can coexist for Davinci platforms. Signed-off-by: Philip, Avinash Cc: Grant Likely Cc: Rob Herring Cc: Rob Landley --- Changes since v1: - Moved TBCLK enable from probe to .pwm_enable & disable from remove to .pwm_disable :100644 100644 07911e6... 927a8ed... M drivers/pwm/pwm-tiehrpwm.c drivers/pwm/pwm-tiehrpwm.c | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 07911e6..927a8ed 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -126,6 +126,7 @@ struct ehrpwm_pwm_chip { void __iomem *mmio_base; unsigned long period_cycles[NUM_PWM_CHANNEL]; enum pwm_polarity polarity[NUM_PWM_CHANNEL]; + struct clk *tbclk; }; static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) @@ -346,6 +347,13 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) /* Channels polarity can be configured from action qualifier module */ configure_polarity(pc, pwm->hwpwm); + /* + * Platforms require explicit clock enabling of TBCLK has + * to enable TBCLK explicitly before enabling PWM device + */ + if (pc->tbclk) + clk_enable(pc->tbclk); + /* Enable time counter for free_run */ ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN); return 0; @@ -374,6 +382,10 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); + /* Disabling TBCLK on PWM disable */ + if (pc->tbclk) + clk_disable(pc->tbclk); + /* Stop Time base counter */ ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT); @@ -464,6 +476,16 @@ static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); return ret; } + + /* Some platforms require explicit tbclk gating */ + if (of_property_read_bool(pdev->dev.of_node, "tbclkgating")) { + pc->tbclk = clk_get(&pdev->dev, "tbclk"); + if (IS_ERR(pc->tbclk)) { + dev_err(&pdev->dev, "Could not get EHRPWM TBCLK\n"); + return PTR_ERR(pc->tbclk); + } + } + pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); if (!(pwmss_submodule_state_change(pdev->dev.parent, EPWMCLK_EN) &