From patchwork Tue Nov 20 05:03:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: avinash philip X-Patchwork-Id: 1770601 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id F214F3FCAE for ; Tue, 20 Nov 2012 05:13:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751582Ab2KTFLv (ORCPT ); Tue, 20 Nov 2012 00:11:51 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:56384 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751238Ab2KTFLu (ORCPT ); Tue, 20 Nov 2012 00:11:50 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id qAK5BS6U006474; Mon, 19 Nov 2012 23:11:29 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id qAK5BSfk024045; Tue, 20 Nov 2012 10:41:28 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Tue, 20 Nov 2012 10:41:28 +0530 Received: from localhost.localdomain (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id qAK5BA2D013430; Tue, 20 Nov 2012 10:41:27 +0530 From: "Philip, Avinash" To: , , , , CC: , , , , , , , , , , "Philip, Avinash" Subject: [PATCH v3 02/10] ARM: am33xx: clk: Add optional clock for EHRPWM Date: Tue, 20 Nov 2012 10:33:43 +0530 Message-ID: <1353387831-31538-3-git-send-email-avinashphilip@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1353387831-31538-1-git-send-email-avinashphilip@ti.com> References: <1353387831-31538-1-git-send-email-avinashphilip@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org EHRPWM module requires explicit clock gating from control module. Hence add clock node in clock tree for EHRPWM modules. Signed-off-by: Philip, Avinash --- :100644 100644 17e3de5... 833260f... M arch/arm/mach-omap2/clock33xx_data.c :100644 100644 a89e825... c0e34e6... M arch/arm/mach-omap2/control.h arch/arm/mach-omap2/clock33xx_data.c | 37 ++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/control.h | 8 +++++++ 2 files changed, 45 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c index 17e3de5..833260f 100644 --- a/arch/arm/mach-omap2/clock33xx_data.c +++ b/arch/arm/mach-omap2/clock33xx_data.c @@ -995,6 +995,40 @@ static struct clk wdt1_fck = { }; /* + * PWMSS Time based module clock node. This node is + * requred to enable clock gating for EHRPWM TBCLK. + */ +static struct clk ehrpwm0_tbclk = { + .name = "ehrpwm0_tbclk", + .clkdm_name = "l4ls_clkdm", + .enable_reg = AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + .enable_bit = AM33XX_PWMSS0_TBCLKEN_SHIFT, + .ops = &clkops_omap2_dflt, + .parent = &l4ls_gclk, + .recalc = &followparent_recalc, +}; + +static struct clk ehrpwm1_tbclk = { + .name = "ehrpwm1_tbclk", + .clkdm_name = "l4ls_clkdm", + .enable_reg = AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + .enable_bit = AM33XX_PWMSS1_TBCLKEN_SHIFT, + .ops = &clkops_omap2_dflt, + .parent = &l4ls_gclk, + .recalc = &followparent_recalc, +}; + +static struct clk ehrpwm2_tbclk = { + .name = "ehrpwm2_tbclk", + .clkdm_name = "l4ls_clkdm", + .enable_reg = AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + .enable_bit = AM33XX_PWMSS2_TBCLKEN_SHIFT, + .ops = &clkops_omap2_dflt, + .parent = &l4ls_gclk, + .recalc = &followparent_recalc, +}; + +/* * clkdev */ static struct omap_clk am33xx_clks[] = { @@ -1074,6 +1108,9 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX), CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), + CLK(NULL, "ehrpwm0_tbclk", &ehrpwm0_tbclk, CK_AM33XX), + CLK(NULL, "ehrpwm1_tbclk", &ehrpwm1_tbclk, CK_AM33XX), + CLK(NULL, "ehrpwm2_tbclk", &ehrpwm2_tbclk, CK_AM33XX), }; int __init am33xx_clk_init(void) diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index a89e825..c0e34e6 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -357,6 +357,14 @@ #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) +/* AM33XX PWMSS Control register */ +#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664 + +/* AM33XX PWMSS Control bitfields */ +#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0 +#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1 +#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2 + /* CONTROL OMAP STATUS register to identify OMAP3 features */ #define OMAP3_CONTROL_OMAP_STATUS 0x044c