From patchwork Tue Nov 20 05:03:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: avinash philip X-Patchwork-Id: 1770761 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 8C00EDF2AB for ; Tue, 20 Nov 2012 05:15:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751230Ab2KTFO4 (ORCPT ); Tue, 20 Nov 2012 00:14:56 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:56681 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750770Ab2KTFOz (ORCPT ); Tue, 20 Nov 2012 00:14:55 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id qAK5EdPo002203; Mon, 19 Nov 2012 23:14:40 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id qAK5EcVB024820; Tue, 20 Nov 2012 10:44:38 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Tue, 20 Nov 2012 10:44:38 +0530 Received: from localhost.localdomain (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id qAK5BA2J013430; Tue, 20 Nov 2012 10:44:38 +0530 From: "Philip, Avinash" To: , , , , CC: , , , , , , , , , , "Philip, Avinash" Subject: [PATCH v3 08/10] pwm: pwm-tiehrpwm: Adding TBCLK gating support. Date: Tue, 20 Nov 2012 10:33:49 +0530 Message-ID: <1353387831-31538-9-git-send-email-avinashphilip@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1353387831-31538-1-git-send-email-avinashphilip@ti.com> References: <1353387831-31538-1-git-send-email-avinashphilip@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Some platforms (like AM33XX) requires clock gating from control module explicitly for TBCLK. Enabling of this clock required for the functioning of the time base sub module in EHRPWM module. So adding optional TBCLK handling. Signed-off-by: Philip, Avinash --- Changes since v2: - Remove DT property for tbclkgating - Use devm_clk_get instead of clk_get Changes since v1: - Moved TBCLK enable from probe to .pwm_enable & disable from remove to .pwm_disable :100644 100644 1cb54aa... 1298f19... M drivers/pwm/pwm-tiehrpwm.c drivers/pwm/pwm-tiehrpwm.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 1cb54aa..1298f19 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -119,6 +119,7 @@ struct ehrpwm_pwm_chip { void __iomem *mmio_base; unsigned long period_cycles[NUM_PWM_CHANNEL]; enum pwm_polarity polarity[NUM_PWM_CHANNEL]; + struct clk *tbclk; }; static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) @@ -339,6 +340,13 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) /* Channels polarity can be configured from action qualifier module */ configure_polarity(pc, pwm->hwpwm); + /* + * Platforms require explicit clock enabling of TBCLK has + * to enable TBCLK explicitly before enabling PWM device + */ + if (pc->tbclk) + clk_enable(pc->tbclk); + /* Enable time counter for free_run */ ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN); return 0; @@ -367,6 +375,10 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); + /* Disabling TBCLK on PWM disable */ + if (pc->tbclk) + clk_disable(pc->tbclk); + /* Stop Time base counter */ ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT); @@ -457,6 +469,10 @@ static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); return ret; } + + /* Populate tbclk entry for platforms require explicit tbclk gating */ + pc->tbclk = devm_clk_get(&pdev->dev, "tbclk"); + pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev);