From patchwork Tue Feb 12 07:32:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: avinash philip X-Patchwork-Id: 2127581 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 3A3113FD4F for ; Tue, 12 Feb 2013 07:32:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756547Ab3BLHbo (ORCPT ); Tue, 12 Feb 2013 02:31:44 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:53431 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755266Ab3BLHbn (ORCPT ); Tue, 12 Feb 2013 02:31:43 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r1C7VXww005126; Tue, 12 Feb 2013 01:31:33 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r1C7VT2A010382; Tue, 12 Feb 2013 13:01:30 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Tue, 12 Feb 2013 13:01:29 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with SMTP id r1C7VPEC014687; Tue, 12 Feb 2013 13:01:26 +0530 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id C3A2F158003; Tue, 12 Feb 2013 13:01:25 +0530 (IST) Received: from ubuntu-psp-linux.india.ext.ti.com (ubuntu-psp-linux [192.168.247.46]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r1C7VNR26332; Tue, 12 Feb 2013 13:01:24 +0530 (IST) From: Philip Avinash To: , , CC: , , , , , , "Philip, Avinash" Subject: [PATCH v2] ARM: AM33XX: clk: Add clock node for EHRPWM TBCLK Date: Tue, 12 Feb 2013 13:02:56 +0530 Message-ID: <1360654376-27057-1-git-send-email-avinashphilip@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: "Philip, Avinash" EHRPWM module requires explicit clock gating of TBCLK from control module. Hence add TBCLK clock node in clock tree for EHRPWM modules. Signed-off-by: Philip Avinash --- Changes since v1: - Remove sparse warnings arch/arm/mach-omap2/cclock33xx_data.c:844:1: warning: Using plain integer as NULL pointer arch/arm/mach-omap2/cclock33xx_data.c:850:1: warning: Using plain integer as NULL pointer arch/arm/mach-omap2/cclock33xx_data.c:856:1: warning: Using plain integer as NULL pointer arch/arm/mach-omap2/cclock33xx_data.c | 30 ++++++++++++++++++++++++++++++ arch/arm/mach-omap2/control.h | 8 ++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index ea64ad6..22387fa 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -832,6 +832,33 @@ static struct clk_hw_omap wdt1_fck_hw = { DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); +static const char *pwmss_clk_parents[] = { + "dpll_per_m2_ck", +}; + +static const struct clk_ops ehrpwm_tbclk_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, +}; + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS0_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS1_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS2_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + /* * clkdev */ @@ -910,6 +937,9 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX), CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), + CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk, CK_AM33XX), + CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk, CK_AM33XX), + CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk, CK_AM33XX), }; diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index 4b05eb9..2fe2812 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -389,6 +389,14 @@ #define AM33XX_DDR_DATA0_IOCTRL 0x1440 #define AM33XX_DDR_DATA1_IOCTRL 0x1444 +/* AM33XX PWMSS Control register */ +#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664 + +/* AM33XX PWMSS Control bitfields */ +#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0 +#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1 +#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2 + /* CONTROL OMAP STATUS register to identify OMAP3 features */ #define OMAP3_CONTROL_OMAP_STATUS 0x044c