From patchwork Thu Apr 4 20:16:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 2394781 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 2D2DBDF25A for ; Thu, 4 Apr 2013 20:16:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764697Ab3DDUQj (ORCPT ); Thu, 4 Apr 2013 16:16:39 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:40487 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1764497Ab3DDUQi (ORCPT ); Thu, 4 Apr 2013 16:16:38 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r34KGSEW030741; Thu, 4 Apr 2013 15:16:28 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r34KGSa3014422; Thu, 4 Apr 2013 15:16:28 -0500 Received: from dlelxv24.itg.ti.com (172.17.1.199) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Thu, 4 Apr 2013 15:16:28 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id r34KGSMk005399; Thu, 4 Apr 2013 15:16:28 -0500 Received: from localhost (h0-54.vpn.ti.com [172.24.0.54]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r34KGRV14506; Thu, 4 Apr 2013 15:16:27 -0500 (CDT) From: Jon Hunter To: Linus Walleij , Grant Likely , Santosh Shilimkar , Kevin Hilman CC: device-tree , linux-omap , linux-arm , Jon Hunter , Felipe Balbi Subject: [PATCH 3/5] gpio/omap: optimise interrupt service routine Date: Thu, 4 Apr 2013 15:16:14 -0500 Message-ID: <1365106576-31816-4-git-send-email-jon-hunter@ti.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1365106576-31816-1-git-send-email-jon-hunter@ti.com> References: <1365106576-31816-1-git-send-email-jon-hunter@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The OMAP GPIO interrupt service routine is checking each bit in the GPIO interrupt status register to see which bits are set. It is not efficient to check every bit especially if only a few bits are set. Therefore, instead of checking every bit use the __ffs() function, which returns the location of the first set bit, to find all the set bits. This optimisation was suggested-by and developed in collaboration with Felipe Balbi. Cc: Felipe Balbi Signed-off-by: Jon Hunter Reviewed-by: Felipe Balbi --- drivers/gpio/gpio-omap.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 5af7acd..685e850 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -689,7 +689,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { void __iomem *isr_reg = NULL; u32 isr; - unsigned int i; + unsigned int bit; struct gpio_bank *bank; int unmasked = 0; struct irq_chip *chip = irq_desc_get_chip(desc); @@ -730,9 +730,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) if (!isr) break; - for (i = 0; isr != 0; isr >>= 1, i++) { - if (!(isr & 1)) - continue; + while (isr) { + bit = __ffs(isr); + isr &= ~(1 << bit); /* * Some chips can't respond to both rising and falling @@ -741,10 +741,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) * to respond to the IRQ for the opposite direction. * This will be indicated in the bank toggle_mask. */ - if (bank->toggle_mask & (1 << i)) - _toggle_gpio_edge_triggering(bank, i); + if (bank->toggle_mask & (1 << bit)) + _toggle_gpio_edge_triggering(bank, bit); - generic_handle_irq(irq_find_mapping(bank->domain, i)); + generic_handle_irq(irq_find_mapping(bank->domain, bit)); } } /* if bank has any level sensitive GPIO pin interrupt