| Message ID | 1365807278-554-4-git-send-email-nm@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2a56428..1c6d969 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -31,6 +31,8 @@ cpu@0 { compatible = "arm,cortex-a9"; next-level-cache = <&L2>; + clocks = <&dpll_mpu>; + clock-names = "cpu"; }; cpu@1 { compatible = "arm,cortex-a9"; @@ -106,6 +108,11 @@ ti,hwmods = "counter_32k"; }; + dpll_mpu: dpll_mpu { + #clock-cells = <0>; + compatible = "ti,omap-clock"; + }; + omap4_pmx_core: pinmux@4a100040 { compatible = "ti,omap4-padconf", "pinctrl-single"; reg = <0x4a100040 0x0196>;
OMAP443x, OMAP446x and OMAP447x platforms use dpll_mpu clock. Add same to common definition. Cc: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> --- RFC of this patch approach for OMAP3 was discussed in http://marc.info/?t=136370325600009&r=1&w=2 along with the detailed context as to why this is an intermediate step. previous revisions of cpufreq-cpu0 support do not use this approach. [Probably belongs to Benoit's tree] arch/arm/boot/dts/omap4.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)