From patchwork Wed May 8 19:06:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 2541281 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id BB2A1DF2E5 for ; Wed, 8 May 2013 19:07:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755257Ab3EHTHA (ORCPT ); Wed, 8 May 2013 15:07:00 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51397 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754517Ab3EHTG4 (ORCPT ); Wed, 8 May 2013 15:06:56 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r48J6LLI008801; Wed, 8 May 2013 14:06:21 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r48J6LjS004256; Wed, 8 May 2013 14:06:21 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Wed, 8 May 2013 14:06:21 -0500 Received: from localhost (kahuna.am.dhcp.ti.com [128.247.91.59]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r48J6LW8015629; Wed, 8 May 2013 14:06:21 -0500 From: Nishanth Menon To: Benoit Cousson , Tony Lindgren , Kevin Hilman , Mike Turquette CC: , , , , Nishanth Menon Subject: [PATCH V5 3/6] ARM: dts: OMAP4: add clock nodes for CPU Date: Wed, 8 May 2013 14:06:13 -0500 Message-ID: <1368039976-29648-4-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1368039976-29648-1-git-send-email-nm@ti.com> References: <1368039976-29648-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org OMAP443x, OMAP446x and OMAP447x platforms use dpll_mpu clock. Add same to common definition. Cc: Benoit Cousson Signed-off-by: Nishanth Menon --- no change in current revision. Previous version: http://marc.info/?l=linux-kernel&m=136580751024225&w=2 arch/arm/boot/dts/omap4.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2a56428..1c6d969 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -31,6 +31,8 @@ cpu@0 { compatible = "arm,cortex-a9"; next-level-cache = <&L2>; + clocks = <&dpll_mpu>; + clock-names = "cpu"; }; cpu@1 { compatible = "arm,cortex-a9"; @@ -106,6 +108,11 @@ ti,hwmods = "counter_32k"; }; + dpll_mpu: dpll_mpu { + #clock-cells = <0>; + compatible = "ti,omap-clock"; + }; + omap4_pmx_core: pinmux@4a100040 { compatible = "ti,omap4-padconf", "pinctrl-single"; reg = <0x4a100040 0x0196>;