From patchwork Fri May 24 19:28:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 2612281 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 6AAFDDF24C for ; Fri, 24 May 2013 19:28:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755292Ab3EXT20 (ORCPT ); Fri, 24 May 2013 15:28:26 -0400 Received: from mail-pb0-f50.google.com ([209.85.160.50]:40422 "EHLO mail-pb0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755041Ab3EXT20 (ORCPT ); Fri, 24 May 2013 15:28:26 -0400 Received: by mail-pb0-f50.google.com with SMTP id wy17so4541129pbc.23 for ; Fri, 24 May 2013 12:28:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=xsg06Qnkc7wsh66dRnlhIyHkVW8ser/hHg9iEfGABh4=; b=PG0qFkycaQiAUp/fmZ6SPdJmIHvei4QLCvvOJfRwHZfjuEFSNkPSuwZC1lo1BKKxYY UHNnR9d/voO+73O/m1S1zNTdXO0ddogy0mj6ac3jgPnYZNzi5hXDPyPTu8hEyjz00Bdg 4kBLOhMrvbwHxITYrKoQUuu3Nb0FYoJ+v1CePCWsTLciRAWYrwPbIzdjL/PQtnpREw9O ntNwkLt/Cd8gnjC3DuVbuJ+G3kci8rpSDNUMiG4dYhHFHA7efw3kEJXY+bm6rIXO/9IN 2nhZBjz5981+D2DfgU/4ARNe5amGuY4jKYp7eL5FzJXkT8XH1Lr7X1sdDnP95vxN7h46 1kZQ== X-Received: by 10.66.233.9 with SMTP id ts9mr19933446pac.15.1369423705604; Fri, 24 May 2013 12:28:25 -0700 (PDT) Received: from localhost (c-24-19-7-36.hsd1.wa.comcast.net. [24.19.7.36]) by mx.google.com with ESMTPSA id sv4sm18609379pab.10.2013.05.24.12.28.23 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 24 May 2013 12:28:24 -0700 (PDT) From: Kevin Hilman To: Tony Lindgren , Benoit Cousson , linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: DTS: OMAP4: Panda/SDP: twl6030: fix mux for IRQ pin and msecure line Date: Fri, 24 May 2013 12:28:22 -0700 Message-Id: <1369423702-31501-1-git-send-email-khilman@linaro.org> X-Mailer: git-send-email 1.8.2 X-Gm-Message-State: ALoCoQn15EHlL1d3NSBXvL4oxLA+Mtgiy12/XMVc9KraVxjFqPfF+Wc31dUz8LCO7++e7ZvylfSX Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Earlier commits ensured proper muxing of pins related to proper TWL6030 behavior: see commit 265a2bc8 (ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled) and commit 1ef43369 (ARM: OMAP4: TWL: mux sys_drm_msecure as output for PMIC). However these only fixed legacy boot and not DT boot. For DT boot, the default mux values need to be set properly in DT. Cc: Tony Lindgren Signed-off-by: Kevin Hilman --- Applies on v3.10-rc2 arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++++++++ arch/arm/boot/dts/omap4-sdp.dts | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 03bd60d..a7a9bc0 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -59,6 +59,7 @@ &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &mcbsp1_pins @@ -66,6 +67,13 @@ &tpd12s015_pins >; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ + 0x14 0x0 /* fref_clk0_out.sys_drm_msecure OUTPUT */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index a35d9cd..5ad0c10 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -145,6 +145,7 @@ &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &dmic_pins @@ -179,6 +180,13 @@ >; }; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ + 0x14 0x0 /* fref_clk0_out.sys_drm_msecure OUTPUT */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */