From patchwork Mon May 27 11:07:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrii Tseglytskyi X-Patchwork-Id: 2619101 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 43FD23FDBC for ; Mon, 27 May 2013 11:08:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757717Ab3E0LHg (ORCPT ); Mon, 27 May 2013 07:07:36 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:56039 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757695Ab3E0LHb (ORCPT ); Mon, 27 May 2013 07:07:31 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r4RB7Urt002063; Mon, 27 May 2013 06:07:30 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r4RB7TDU027110; Mon, 27 May 2013 06:07:30 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Mon, 27 May 2013 06:07:29 -0500 Received: from localhost (uglx0174653.ucm2.emeaucm.ext.ti.com [10.167.145.64]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r4RB7S18026764; Mon, 27 May 2013 06:07:29 -0500 From: Andrii Tseglytskyi To: Kevin Hilman , J Keerthy CC: , Subject: [PATCH v1 1/3] PM / AVS: SmartReflex: disable errgen before vpbound disable Date: Mon, 27 May 2013 14:07:24 +0300 Message-ID: <1369652846-14412-2-git-send-email-andrii.tseglytskyi@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1369652846-14412-1-git-send-email-andrii.tseglytskyi@ti.com> References: <1369652846-14412-1-git-send-email-andrii.tseglytskyi@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Nishanth Menon vpboundsintr_en is available inside the IP block as an re-sycned version and one which is not. Due to this, there is an 1 sysclk cycle window where interruptz could be asserted low for 1 cycle. IF, intr_en is cleared on the exact same cycle as the irqclr, an additional pulse is generated which indicates for VP that an additional adjustment of voltage is required. This results in VP doing two voltage adjustments for the SRERR (based on configuration, upto 4 steps), instead of the needed 1 step. Due to the unexpected pulse from AVS which breaks the AVS-VP communication protocol, VP also ends up in a stuck condition by entering a state where VP module remains non-responsive to any futher AVS adjustment events. This creates the symptom called "TRANXDONE Timeout" scenario. By disabling errgen prior to disable of intr_en, this situation can be avoided. Signed-off-by: Vincent Bour Signed-off-by: Leonardo Affortunati Signed-off-by: Nishanth Menon Signed-off-by: Andrii.Tseglytskyi --- drivers/power/avs/smartreflex.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c index 6b2238b..f34d34d 100644 --- a/drivers/power/avs/smartreflex.c +++ b/drivers/power/avs/smartreflex.c @@ -449,12 +449,17 @@ int sr_disable_errgen(struct voltagedomain *voltdm) return -EINVAL; } - /* Disable the interrupts of ERROR module */ - sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0); - /* Disable the Sensor and errorgen */ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0); + /* + * Disable the interrupts of ERROR module + * NOTE: modify is a read, modify,write - an implicit OCP barrier + * which is required is present here - sequencing is critical + * at this point (after errgen is disabled, vpboundint disable) + */ + sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0); + return 0; }