From patchwork Wed Jun 5 06:46:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: R Sricharan X-Patchwork-Id: 2665291 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id D9CAADFE82 for ; Wed, 5 Jun 2013 06:46:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752132Ab3FEGqs (ORCPT ); Wed, 5 Jun 2013 02:46:48 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:58620 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752208Ab3FEGqo (ORCPT ); Wed, 5 Jun 2013 02:46:44 -0400 Received: from dbdlxv05.itg.ti.com ([172.24.171.60]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r556kIFU018288; Wed, 5 Jun 2013 01:46:18 -0500 Received: from DBDE73.ent.ti.com (dbde73.ent.ti.com [172.24.171.98]) by dbdlxv05.itg.ti.com (8.14.3/8.13.8) with ESMTP id r556kFcK012990; Wed, 5 Jun 2013 01:46:16 -0500 Received: from dbdp33.itg.ti.com (172.24.170.252) by DBDE73.ent.ti.com (172.24.171.98) with Microsoft SMTP Server id 14.2.342.3; Wed, 5 Jun 2013 14:46:15 +0800 Received: from uda0393807.apr.dhcp.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp33.itg.ti.com (8.13.8/8.13.8) with ESMTP id r556kCjf014924; Wed, 5 Jun 2013 12:16:15 +0530 From: Sricharan R To: , CC: , , , , Roger Quadros Subject: [PATCH 2/4] ARM: dts: omap5-uevm: Add USB Host support Date: Wed, 5 Jun 2013 12:16:08 +0530 Message-ID: <1370414770-1485-3-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1370414770-1485-1-git-send-email-r.sricharan@ti.com> References: <1370414770-1485-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Roger Quadros Provide the RESET regulators for the USB PHYs, the USB Host port modes and the PHY devices. Also provide pin multiplexer information for the USB host pins. Cc: Roger Quadros Signed-off-by: Roger Quadros [Sricharan R : Replaced constants with preprocessor macros] Signed-off-by: Sricharan R --- arch/arm/boot/dts/omap5-uevm.dts | 77 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap5.dtsi | 30 +++++++++++++++ 2 files changed, 107 insertions(+) diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 843a001..cf862df 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -25,6 +25,47 @@ regulator-max-microvolt = <3000000>; }; + /* HS USB Port 2 RESET */ + hsusb2_reset: hsusb2_reset_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-supply = <&hsusb2_reset>; + }; + + /* HS USB Port 3 RESET */ + hsusb3_reset: hsusb3_reset_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb3_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */ + startup-delay-us = <70000>; + enable-active-high; + }; + + /* HS USB Host PHY on PORT 3 */ + hsusb3_phy: hsusb3_phy { + compatible = "usb-nop-xceiv"; + reset-supply = <&hsusb3_reset>; + }; + + /* hsusb2_phy is clocked by FREF_CLK1 i.e. auxclk1 */ + clock_alias { + clock-name = "auxclk1_ck"; + clock-alias = "main_clk"; + device = <&hsusb2_phy>; + clock-frequency = <19200000>; /* 19.2 MHz */ + }; }; &omap5_pmx_core { @@ -35,6 +76,7 @@ &dmic_pins &mcbsp1_pins &mcbsp2_pins + &usbhost_pins >; twl6040_pins: pinmux_twl6040_pins { @@ -120,6 +162,32 @@ 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ >; }; + + usbhost_pins: pinmux_usbhost_pins { + pinctrl-single,pins = < + 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe INPUT | MODE 0 */ + 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data INPUT | MODE 0 */ + + 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe INPUT | MODE 0 */ + 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data INPUT | MODE 0 */ + + 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 OUTPUT | MODE 6 HUB_NRESET */ + 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 OUTPUT | MODE 6 ETH_NRESET */ + >; + }; +}; + +&omap5_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &usbhost_wkup_pins + >; + + usbhost_wkup_pins: pinmux_usbhost_wkup_pins { + pinctrl-single,pins = < + 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out OUTPUT | MODE 7 for USB hub clk */ + >; + }; }; &mmc1 { @@ -164,6 +232,15 @@ status = "disabled"; }; +&usbhshost { + port2-mode = "ehci-hsic"; + port3-mode = "ehci-hsic"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy &hsusb3_phy>; +}; + &mcspi1 { }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 1e84db8..67d6e1f 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -666,5 +666,35 @@ ctrl-module = <&omap_control_usb>; }; }; + + usbhstll: usbhstll@4a062000 { + compatible = "ti,usbhs-tll"; + reg = <0x4a062000 0x1000>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "usb_tll_hs"; + }; + + usbhshost: usbhshost@4a064000 { + compatible = "ti,usbhs-host"; + reg = <0x4a064000 0x800>; + ti,hwmods = "usb_host_hs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbhsohci: ohci@4a064800 { + compatible = "ti,ohci-omap3", "usb-ohci"; + reg = <0x4a064800 0x400>; + interrupt-parent = <&gic>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; + }; + + usbhsehci: ehci@4a064c00 { + compatible = "ti,ehci-omap", "usb-ehci"; + reg = <0x4a064c00 0x400>; + interrupt-parent = <&gic>; + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; + }; + }; }; };