From patchwork Thu Jun 27 08:38:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 2790631 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B80DB9F3A0 for ; Thu, 27 Jun 2013 08:39:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 758EF2023A for ; Thu, 27 Jun 2013 08:39:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12B4B2023D for ; Thu, 27 Jun 2013 08:39:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752938Ab3F0IjU (ORCPT ); Thu, 27 Jun 2013 04:39:20 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:53597 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752426Ab3F0IjT (ORCPT ); Thu, 27 Jun 2013 04:39:19 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r5R8cu3s024406; Thu, 27 Jun 2013 03:38:56 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r5R8cuWv002250; Thu, 27 Jun 2013 03:38:56 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Thu, 27 Jun 2013 03:38:55 -0500 Received: from sokoban.tieu.ti.com (h79-12.vpn.ti.com [172.24.79.12]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r5R8chFF017521; Thu, 27 Jun 2013 03:38:54 -0500 From: Tero Kristo To: , , , , , CC: , Subject: [PATCH 4/4] ARM: DRA7: clockdomain data: add init file for dra7 Date: Thu, 27 Jun 2013 11:38:19 +0300 Message-ID: <1372322299-25046-5-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1372322299-25046-1-git-send-email-t-kristo@ti.com> References: <1372322299-25046-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP cclock7xx_data.c now contains only init function and the clkdev mapping that is still needed by some drivers. Eventually most of this file can be removed, once a common location for the clk init can be found, and the clkdev mapping is no longer needed. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/cclock7xx_data.c | 93 ++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 arch/arm/mach-omap2/cclock7xx_data.c diff --git a/arch/arm/mach-omap2/cclock7xx_data.c b/arch/arm/mach-omap2/cclock7xx_data.c new file mode 100644 index 0000000..dba528a --- /dev/null +++ b/arch/arm/mach-omap2/cclock7xx_data.c @@ -0,0 +1,83 @@ +/* + * DRA7xx Clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Mike Turquette (mturquette@linaro.org) + * Tero Kristo (t-kristo@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include "soc.h" +#include "clock.h" + +#define DRA7_DPLL_ABE_DEFFREQ 361267200 +#define DRA7_DPLL_GMAC_DEFFREQ 1000000000 + +/* + * clkdev + */ + +static struct omap_dt_clk dra7xx_clks[] = { + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), + DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK(NULL, "sys_clkin", "sys_clkin1"), +}; + +int __init dra7xx_clk_init(void) +{ + struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; + int rc; + /* + * Must stay commented until all OMAP SoC drivers are + * converted to runtime PM, or drivers may start crashing + * + * omap2_clk_disable_clkdm_control(); + */ + + dt_omap_clk_init(); + + omap_dt_clocks_register(dra7xx_clks, ARRAY_SIZE(dra7xx_clks)); + + omap2_clk_disable_autoidle_all(); + + abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux"); + sys_clkin2 = clk_get_sys(NULL, "sys_clkin2"); + dpll_ck = clk_get_sys(NULL, "dpll_abe_ck"); + + rc = clk_set_parent(abe_dpll_mux, sys_clkin2); + if (!rc) + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); + if (rc) + pr_err("%s: failed to configure ABE DPLL!\n", __func__); + + dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); + rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); + if (rc) + pr_err("%s: failed to configure GMAC DPLL!\n", __func__); + + return 0; +}