From patchwork Thu Jul 18 16:43:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: R Sricharan X-Patchwork-Id: 2829712 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B3988C0AB2 for ; Thu, 18 Jul 2013 16:45:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 95184201D3 for ; Thu, 18 Jul 2013 16:45:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 49BFA201BD for ; Thu, 18 Jul 2013 16:45:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759215Ab3GRQog (ORCPT ); Thu, 18 Jul 2013 12:44:36 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:57012 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759213Ab3GRQoe (ORCPT ); Thu, 18 Jul 2013 12:44:34 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r6IGi23q028728; Thu, 18 Jul 2013 11:44:02 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r6IGi2OA009863; Thu, 18 Jul 2013 11:44:02 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Thu, 18 Jul 2013 11:44:02 -0500 Received: from localhost.localdomain (uda0393807.apr.dhcp.ti.com [172.24.145.242]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r6IGhphG018646; Thu, 18 Jul 2013 11:43:59 -0500 From: Sricharan R To: , , , , CC: , , , , , Subject: [PATCH 2/3] ARM: dts: DRA: Add crossbar device binding Date: Thu, 18 Jul 2013 22:13:49 +0530 Message-ID: <1374165830-6367-3-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1374165830-6367-1-git-send-email-r.sricharan@ti.com> References: <1374165830-6367-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the irq/dma crossbar device nodes. There is a IRQ and DMA crossbar device in the soc, which maps the irq/dma requests from the peripherals to the mpu/dsp/ipu/eve interrupt and sdma/edma controller's inputs. The Peripheral irq/dma requests are connected to only one crossbar input and the output of the crossbar is connected to only one controller's input line. On POR, there are some mappings which are done by default. Those peripherals which do not have a mapping on POR, should be configured to route its requests using the crossbar control registers. The irq/dma mapping for some peripherals are added with the crossbar nodes here. Signed-off-by: Sricharan R --- arch/arm/boot/dts/dra7.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index a5d9350..e6208b4 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -85,6 +85,25 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2"; + crossbar_mpu: mpuirq@4a002a48 { + compatible = "crossbar"; + crossbar-name = "mpu-irq"; + reg = <0x4a002a48 0x0130>; + reg-width = <16>; + crossbar-lines = "mpu-irq", "rtc-ss-alarm", <0x9f 0xd9 0x12c>, + "mpu-irq", "mcasp3-arevt", <0x9e 0x96 0x12a>, + "mpu-irq", "mcasp3-axevt", <0x9d 0x97 0x128>; + }; + + crossbar_dma: dmareq@4a002b78 { + compatible = "crossbar"; + crossbar-name = "dma-req"; + reg = <0x4a002b78 0x0100>; + reg-width = <16>; + crossbar-lines = "dma-req", "mcasp3-rx", <0x7e 0x84 0xfc>, + "dma-req", "mcasp3-tx", <0x7d 0x85 0xfa>; + }; + counter32k: counter@4ae04000 { compatible = "ti,omap-counter32k"; reg = <0x4ae04000 0x40>;