From patchwork Fri Aug 2 16:25:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 2838044 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B03F0BF535 for ; Fri, 2 Aug 2013 16:27:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7AF34202AB for ; Fri, 2 Aug 2013 16:27:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3713E20259 for ; Fri, 2 Aug 2013 16:27:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754713Ab3HBQ1m (ORCPT ); Fri, 2 Aug 2013 12:27:42 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:50399 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753924Ab3HBQ1k (ORCPT ); Fri, 2 Aug 2013 12:27:40 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r72GRAMV003558; Fri, 2 Aug 2013 11:27:10 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r72GRALn014362; Fri, 2 Aug 2013 11:27:10 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Fri, 2 Aug 2013 11:27:09 -0500 Received: from sokoban.tieu.ti.com (h78-17.vpn.ti.com [172.24.78.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r72GQ2Tp003114; Fri, 2 Aug 2013 11:27:08 -0500 From: Tero Kristo To: , , , , , CC: , Subject: [PATCHv5 28/31] ARM: dts: AM35xx clock data Date: Fri, 2 Aug 2013 19:25:47 +0300 Message-ID: <1375460751-23676-29-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375460751-23676-1-git-send-email-t-kristo@ti.com> References: <1375460751-23676-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch creates a unique node for each AM35xx specific clock in the AM35xx power, reset and clock manager (PRCM). Most of the AM35xx clock data is shared with OMAP3xxx, this patch only creates the delta. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am35xx-clocks.dtsi | 113 ++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 arch/arm/boot/dts/am35xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi new file mode 100644 index 0000000..d28aa5c --- /dev/null +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -0,0 +1,113 @@ +/* + * Device Tree Source for AM35xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +ipss_ick: ipss_ick@48004a10 { + #clock-cells = <0>; + compatible = "ti,interface-clock"; + clocks = <&core_l3_ick>; + reg = <0x48004a10 0x4>; + ti,clkdm-name = "core_l3_clkdm"; + ti,enable-bit = <4>; + ti,am35xx-clk; +}; + +rmii_ck: rmii_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; +}; + +pclk_ck: pclk_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; +}; + +emac_ick: emac_ick@4800259c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&ipss_ick>; + reg = <0x4800259c 0x4>; + ti,clkdm-name = "core_l3_clkdm"; + ti,enable-bit = <1>; + ti,am35xx-clk; +}; + +emac_fck: emac_fck@4800259c { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&rmii_ck>; + reg = <0x4800259c 0x4>; + bit-shift = <9>; +}; + +vpfe_ick: vpfe_ick@4800259c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&ipss_ick>; + reg = <0x4800259c 0x4>; + ti,clkdm-name = "core_l3_clkdm"; + ti,enable-bit = <2>; + ti,am35xx-clk; +}; + +vpfe_fck: vpfe_fck@4800259c { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&pclk_ck>; + reg = <0x4800259c 0x4>; + bit-shift = <10>; +}; + +hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@4800259c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&ipss_ick>; + reg = <0x4800259c 0x4>; + ti,clkdm-name = "core_l3_clkdm"; + ti,enable-bit = <0>; + ti,am35xx-clk; +}; + +hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@4800259c { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_ck>; + reg = <0x4800259c 0x4>; + bit-shift = <8>; +}; + +hecc_ck: hecc_ck@4800259c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_ck>; + reg = <0x4800259c 0x4>; + ti,clkdm-name = "core_l3_clkdm"; + ti,enable-bit = <3>; + ti,am35xx-clk; +}; + +uart4_ick_am35xx: uart4_ick_am35xx@48004a10 { + #clock-cells = <0>; + compatible = "ti,interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x48004a10 0x4>; + ti,clkdm-name = "core_l4_clkdm"; + ti,enable-bit = <23>; +}; + +uart4_fck_am35xx: uart4_fck_am35xx@48004a00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x48004a00 0x4>; + ti,clkdm-name = "core_l4_clkdm"; + ti,enable-bit = <23>; +};