From patchwork Thu Aug 29 13:16:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 2851318 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B39A2BF546 for ; Thu, 29 Aug 2013 13:18:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9C3422030D for ; Thu, 29 Aug 2013 13:18:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E10A7201CB for ; Thu, 29 Aug 2013 13:18:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754455Ab3H2NSA (ORCPT ); Thu, 29 Aug 2013 09:18:00 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:47989 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754403Ab3H2NR7 (ORCPT ); Thu, 29 Aug 2013 09:17:59 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r7TDHPRV010480; Thu, 29 Aug 2013 08:17:25 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r7TDHPdB028881; Thu, 29 Aug 2013 08:17:25 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Thu, 29 Aug 2013 08:17:25 -0500 Received: from sokoban.tieu.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id r7TDGkK8002988; Thu, 29 Aug 2013 08:17:22 -0500 From: Tero Kristo To: , , , , , CC: , , Keerthy Subject: [PATCHv6 15/45] ARM: dts: DRA7: Add PCIe related clock nodes Date: Thu, 29 Aug 2013 16:16:07 +0300 Message-ID: <1377782197-10611-16-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377782197-10611-1-git-send-email-t-kristo@ti.com> References: <1377782197-10611-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Keerthy This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk which are used by PCIe phy. It also adds a mux clock to choose the source of optfclk_pciephy_div_clk clock. Signed-off-by: Keerthy Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 397a60a..6a53d3b 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -2061,3 +2061,27 @@ vip3_gclk_mux: vip3_gclk_mux@4a009030 { reg = <0x4a009030 0x4>; bit-mask = <0x1>; }; + +optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { + compatible = "divider-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x4a00821c 0x4>; + bit-mask = <0x100>; +}; + +optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { + compatible = "gate-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x4a0093b0 0x4>; + bit-shift = <9>; +}; + +optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { + compatible = "gate-clock"; + clocks = <&optfclk_pciephy_div>; + #clock-cells = <0>; + reg = <0x4a0093b0 0x4>; + bit-shift = <10>; +};