From patchwork Thu Aug 29 13:16:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 2851337 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 24FF4BF546 for ; Thu, 29 Aug 2013 13:19:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 709A3201C8 for ; Thu, 29 Aug 2013 13:19:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 19783201E9 for ; Thu, 29 Aug 2013 13:18:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754802Ab3H2NSm (ORCPT ); Thu, 29 Aug 2013 09:18:42 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:49158 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754693Ab3H2NSl (ORCPT ); Thu, 29 Aug 2013 09:18:41 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r7TDHqFh015454; Thu, 29 Aug 2013 08:17:52 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r7TDHq9Q029308; Thu, 29 Aug 2013 08:17:52 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Thu, 29 Aug 2013 08:17:52 -0500 Received: from sokoban.tieu.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id r7TDGkKK002988; Thu, 29 Aug 2013 08:17:50 -0500 From: Tero Kristo To: , , , , , CC: , Subject: [PATCHv6 27/45] ARM: dts: AM35xx clock data Date: Thu, 29 Aug 2013 16:16:19 +0300 Message-ID: <1377782197-10611-28-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377782197-10611-1-git-send-email-t-kristo@ti.com> References: <1377782197-10611-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch creates a unique node for each AM35xx specific clock in the AM35xx power, reset and clock manager (PRCM). Most of the AM35xx clock data is shared with OMAP3xxx, this patch only creates the delta. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am35xx-clocks.dtsi | 101 ++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 arch/arm/boot/dts/am35xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi new file mode 100644 index 0000000..7749413 --- /dev/null +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -0,0 +1,101 @@ +/* + * Device Tree Source for AM35xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +ipss_ick: ipss_ick@48004a10 { + #clock-cells = <0>; + compatible = "ti,am35xx-interface-clock"; + clocks = <&core_l3_ick>; + reg = <0x48004a10 0x4>; + ti,enable-bit = <4>; +}; + +rmii_ck: rmii_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; +}; + +pclk_ck: pclk_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; +}; + +emac_ick: emac_ick@4800259c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x4800259c 0x4>; + ti,enable-bit = <1>; +}; + +emac_fck: emac_fck@4800259c { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&rmii_ck>; + reg = <0x4800259c 0x4>; + bit-shift = <9>; +}; + +vpfe_ick: vpfe_ick@4800259c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x4800259c 0x4>; + ti,enable-bit = <2>; +}; + +vpfe_fck: vpfe_fck@4800259c { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&pclk_ck>; + reg = <0x4800259c 0x4>; + bit-shift = <10>; +}; + +hsotgusb_ick: hsotgusb_ick@4800259c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x4800259c 0x4>; + ti,enable-bit = <0>; +}; + +hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@4800259c { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&sys_ck>; + reg = <0x4800259c 0x4>; + bit-shift = <8>; +}; + +hecc_ck: hecc_ck@4800259c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&sys_ck>; + reg = <0x4800259c 0x4>; + ti,enable-bit = <3>; +}; + +uart4_ick_am35xx: uart4_ick_am35xx@48004a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x48004a10 0x4>; + ti,enable-bit = <23>; +}; + +uart4_fck_am35xx: uart4_fck_am35xx@48004a00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x48004a00 0x4>; + ti,enable-bit = <23>; +};