From patchwork Wed Sep 18 16:02:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: R Sricharan X-Patchwork-Id: 2907761 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 310A3BFF05 for ; Wed, 18 Sep 2013 16:03:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BD8CE2016A for ; Wed, 18 Sep 2013 16:03:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 39E0B20394 for ; Wed, 18 Sep 2013 16:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752083Ab3IRQDR (ORCPT ); Wed, 18 Sep 2013 12:03:17 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:36836 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751652Ab3IRQDR (ORCPT ); Wed, 18 Sep 2013 12:03:17 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r8IG2lph031831; Wed, 18 Sep 2013 11:02:47 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8IG2l7t013809; Wed, 18 Sep 2013 11:02:47 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Wed, 18 Sep 2013 11:02:47 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8IG2hLD011422; Wed, 18 Sep 2013 11:02:44 -0500 From: Sricharan R To: , CC: , , , , , , Subject: [PATCH V4] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register Date: Wed, 18 Sep 2013 21:32:42 +0530 Message-ID: <1379520162-31932-1-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The realtime counter called master counter, produces the count used by the private timer peripherals in the MPU_CLUSTER. The CNTFRQ per cpu register is used to denote the frequency of the counter. Currently the frequency value is passed from the DT file, but this is not scalable when we have other non-DT guest OS. This register must be set to the right value by the secure rom code. Setting this register helps in propagating the right frequency value across OSes. More discussions and the reason for adding this in a non-DT way can be seen from below. http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html So configuring this secure register for all the cpus here. While here, removing the clock-frequency DT entry for omap5 as it is no more needed after this patch. Cc: Santosh Shilimkar Cc: Nishanth Menon Cc: Rajendra Nayak Cc: Marc Zyngier Cc: Mark Rutland Tested-by: Nishanth Menon Acked-by: Santosh Shilimkar Signed-off-by: Sricharan R --- [V4] Updated commit log, removed the redundant entry in OMAP5.dtsi and a unnecessary newline in timer.c arch/arm/boot/dts/omap5.dtsi | 1 - arch/arm/mach-omap2/omap-secure.h | 2 ++ arch/arm/mach-omap2/omap-smp.c | 9 +++++++++ arch/arm/mach-omap2/timer.c | 5 +++++ 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 07be2cd..8a45512 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -52,7 +52,6 @@ , , ; - clock-frequency = <6144000>; }; gic: interrupt-controller@48211000 { diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 0e72917..5f88824 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -42,6 +42,8 @@ #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 +#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 + /* Secure PPA(Primary Protected Application) APIs */ #define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 8708b2a..5a3c8d3 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -41,6 +41,8 @@ u16 pm44xx_errata; +extern unsigned long arch_timer_freq; + /* SCU base address */ static void __iomem *scu_base; @@ -66,6 +68,13 @@ static void omap4_secondary_init(unsigned int cpu) 4, 0, 0, 0, 0, 0); /* + * Configure the CNTFRQ register for the secondary cpu's which + * indicates the frequency of the cpu local timers. + */ + if (soc_is_omap54xx() || soc_is_dra7xx()) + omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); + + /* * Synchronise with the boot thread. */ spin_lock(&boot_lock); diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index fa74a06..d0af9b2 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -55,6 +55,7 @@ #include "soc.h" #include "common.h" #include "powerdomain.h" +#include "omap-secure.h" #define REALTIME_COUNTER_BASE 0x48243200 #define INCREMENTER_NUMERATOR_OFFSET 0x10 @@ -65,6 +66,7 @@ static struct omap_dm_timer clkev; static struct clock_event_device clockevent_gpt; +unsigned long arch_timer_freq; static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) { @@ -542,6 +544,9 @@ static void __init realtime_counter_init(void) reg |= den; __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); + arch_timer_freq = (rate / den) * num; + omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); + iounmap(base); } #else