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[78.128.193.202]) by mx.google.com with ESMTPSA id a43sm5709599eep.9.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Sep 2013 13:08:09 -0700 (PDT) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Matt Mackall , Herbert Xu , Tony Lindgren , Russell King Cc: linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Pali=20Roh=C3=A1r?= Subject: [PATCH 2/2] RX-51: Add support for OMAP3 ROM Random Number Generator Date: Wed, 18 Sep 2013 22:05:57 +0200 Message-Id: <1379534757-20870-3-git-send-email-pali.rohar@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1379534757-20870-1-git-send-email-pali.rohar@gmail.com> References: <201303281854.02847@pali> <1379534757-20870-1-git-send-email-pali.rohar@gmail.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Pali Rohár --- arch/arm/mach-omap2/board-rx51.c | 10 ++++++++++ arch/arm/mach-omap2/omap-secure.c | 11 +++++++++++ arch/arm/mach-omap2/omap-secure.h | 1 + 3 files changed, 22 insertions(+) diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index db168c9..c2a3e39 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -93,6 +93,14 @@ static struct omap_musb_board_data musb_board_data = { .power = 0, }; +static struct platform_device omap3_rom_rng_device = { + .name = "omap_rng", + .id = -1, + .dev = { + .platform_data = rx51_secure_rng_call, + }, +}; + static void __init rx51_init(void) { struct omap_sdrc_params *sdrc_params; @@ -113,6 +121,8 @@ static void __init rx51_init(void) /* set IBE to 1 */ rx51_secure_update_aux_cr(BIT(6), 0); #endif + pr_info("RX-51: Registring OMAP3 HWRNG device\n"); + platform_device_register(&omap3_rom_rng_device); } /* Ensure SDRC pins are mux'd for self-refresh */ diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 146a7c4..5ac122e 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -135,3 +135,14 @@ u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) FLAG_START_CRITICAL, 1, acr, 0, 0, 0); } + +/** + * rx51_secure_rng_call: Routine for HW random generator + */ +u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) +{ + return rx51_secure_dispatcher(RX51_PPA_HWRNG, + 0, + NO_FLAG, + 3, ptr, count, flag, 0); +} diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 51b59c6..f6cabb0 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -65,6 +65,7 @@ extern int omap_secure_ram_reserve_memblock(void); extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, u32 arg1, u32 arg2, u32 arg3, u32 arg4); extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); +extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); #ifdef CONFIG_OMAP4_ERRATA_I688 extern int omap_barrier_reserve_memblock(void);