From patchwork Fri Oct 18 06:42:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Witcher X-Patchwork-Id: 3074001 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1F7EFBF924 for ; Sun, 20 Oct 2013 21:02:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 57C8820334 for ; Sun, 20 Oct 2013 21:02:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 236D420303 for ; Sun, 20 Oct 2013 21:02:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751891Ab3JTVCv (ORCPT ); Sun, 20 Oct 2013 17:02:51 -0400 Received: from elasmtp-mealy.atl.sa.earthlink.net ([209.86.89.69]:38496 "EHLO elasmtp-mealy.atl.sa.earthlink.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751783Ab3JTVCu (ORCPT ); Sun, 20 Oct 2013 17:02:50 -0400 X-Greylist: delayed 973 seconds by postgrey-1.27 at vger.kernel.org; Sun, 20 Oct 2013 17:02:50 EDT DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=dk20050327; d=mindspring.com; b=jiLvaFNSv42zmIl+BTjoKMR57SYvr5W/RQb9jRZ2LEAZwAvLiCn7XOmCRE0l44M7; h=Received:From:To:Subject:Date:Message-Id:X-Mailer:X-ELNK-Trace:X-Originating-IP; Received: from [98.66.211.235] (helo=localhost.localdomain) by elasmtp-mealy.atl.sa.earthlink.net with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.67) (envelope-from ) id 1VXztU-0003B2-9I; Sun, 20 Oct 2013 16:46:36 -0400 From: Eric Witcher To: nm@ti.com, bcousson@baylibre.com, linux-omap@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH] ARM: dts: omap5-uevm: fix mcspi node pin descriptions Date: Fri, 18 Oct 2013 02:42:34 -0400 Message-Id: <1382078554-31628-1-git-send-email-ewitcher@mindspring.com> X-Mailer: git-send-email 1.7.11.7 X-ELNK-Trace: dfac6e4f32b09e339c7f779228e2f6aeda0071232e20db4d260dbdf2a752c64376394b66da1a0e7f350badd9bab72f9c350badd9bab72f9c350badd9bab72f9c X-Originating-IP: 98.66.211.235 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Correct mcspi pin descriptions to match corresponding node name and add chip select number to be consistent with OMAP5 TRM. Signed-off-by: Eric Witcher --- arch/arm/boot/dts/omap5-uevm.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index d784b3a..90c7843 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -131,25 +131,25 @@ 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ - 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ + 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ >; }; mcspi3_pins: pinmux_mcspi3_pins { pinctrl-single,pins = < - 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ - 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ - 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ - 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ + 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ + 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ + 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ + 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ >; }; mcspi4_pins: pinmux_mcspi4_pins { pinctrl-single,pins = < - 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ - 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ - 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ - 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ + 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi4_clk */ + 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi4_simo */ + 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi4_somi */ + 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi4_cs0 */ >; };