From patchwork Fri Dec 13 09:12:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 3339191 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6CE049F380 for ; Fri, 13 Dec 2013 09:14:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1F4BB207F8 for ; Fri, 13 Dec 2013 09:14:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 09550207F9 for ; Fri, 13 Dec 2013 09:14:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752221Ab3LMJOa (ORCPT ); Fri, 13 Dec 2013 04:14:30 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:46750 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751636Ab3LMJO2 (ORCPT ); Fri, 13 Dec 2013 04:14:28 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id rBD9Dkft011188; Fri, 13 Dec 2013 03:13:46 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id rBD9DkZY005565; Fri, 13 Dec 2013 03:13:46 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Fri, 13 Dec 2013 03:13:46 -0600 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id rBD9DQ6D008709; Fri, 13 Dec 2013 03:13:40 -0600 From: Pekon Gupta To: Brian Norris , Artem Bityutskiy , Scott Wood , Tom Rini CC: , , linux-omap , Enric Balletbo Serra , Stefan Roese , Javier Martinez Canillas , Thomas Petazzoni , Igor Grinberg , Michael Trimarchi , , , Nikita Kiryanov , , , Ezequiel Garcia , , , Pekon Gupta Subject: [PATCH v1 2/2] mtd: nand: omap: fix ecclayout to be in sync with u-boot NAND driver Date: Fri, 13 Dec 2013 14:42:58 +0530 Message-ID: <1386925978-23705-3-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1386925978-23705-1-git-send-email-pekon@ti.com> References: <1386925978-23705-1-git-send-email-pekon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch mainly fixes ecc-layout for following ecc-schemes, to bring them in sync with u-boot omap_gpmc NAND driver: - BCH4_SW: OMAP_ECC_BCH4_CODE_HW_DETECTION_SW This ecc-scheme is mainly used on AM35xx and other legacy platforms. - BCH8_SW: OMAP_ECC_BCH8_CODE_HW_DETECTION_SW This ecc-scheme is mainly used on OMAP3x and other legacy platforms. Apart from above, this patch also touches other ecc-schemes as the fix required refactoring common code, into ecc-scheme specific code. Hence, end-to-end NAND boot sequence was tested on AM335x-EVM to avoid any further regression on legacy or current platforms. (BCH8_HW) (HAM1_HW) (HAM1_HW) (HAM1_HW) (UBIFS) ROM ---------> SPL ---------> U-Boot ---------> Kernel ---------> File-System (BCH8_HW) (BCH8_SW) (BCH8_SW) (BCH8_SW) (UBIFS) ROM ---------> SPL ---------> U-Boot ---------> Kernel ---------> File-System (BCH8_HW) (BCH8_HW) (BCH8_HW) (BCH8_HW) (UBIFS) ROM ---------> SPL ---------> U-Boot ---------> Kernel ---------> File-System *Configurations used to build u-boot and kernel for end-to-end NAND boot* +------------+--------------------------------------------+------------------+ | ecc-scheme | u-boot/SPL configs | kernel DTS | +------------+--------------------------------------------+------------------+ | | | | | HAM1_HW | #define CONFIG_NAND_OMAP_ECCSCHEME \ |ti,nand-ecc-opts= | | | OMAP_ECC_HAM1_CODE_HW | "ham1" | | (1-bit | #define CONFIG_SYS_NAND_ECCBYTES 3 | | | Hamming | #define CONFIG_SYS_NAND_ECCPOS \ | | | using h/w) | { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ | | | | 10, 11, 12 } | | | | (for NAND page-size=2048) | | | | | | +------------+--------------------------------------------+------------------+ | | | | | BCH8_SW | #define CONFIG_NAND_OMAP_ECCSCHEME \ |ti,nand-ecc-opts= | | | OMAP_ECC_BCH8_CODE_HW_DETECTION_SW | "bch8" | |(8-bit BCH | #define CONFIG_SYS_NAND_ECCBYTES 13 |(without ELM node)| | using s/w | #define CONFIG_BCH | | |library for | #undef CONFIG_SPL_NAND_AM33XX_BCH | | |for ECC | #define CONFIG_SPL_NAND_SIMPLE | | | error | #define CONFIG_SYS_NAND_ECCPOS \ | | |correction) | {2, 3, 4, 5, 6, 7, 8, 9, 10, \ | | | | 11, 12, 13, 14, \ | | | | 16, 17, 18, 19, 20, 21, 22, 23, 24, \ | | | | 25, 26, 27, 28, \ | | | | 30, 31, 32, 33, 34, 35, 36, 37, 38, \ | | | | 39, 40, 41, 42, \ | | | | 44, 45, 46, 47, 48, 49, 50, 51, 52, \ | | | | 53, 54, 55, 56, } | | | | (for NAND page-size=2048) | | | | #define CONFIG_SYS_NAND_ECCSIZE 512 | | | | | | +------------+--------------------------------------------+------------------+ | | | | | BCH8_HW | #define CONFIG_NAND_OMAP_ECCSCHEME \ |ti,nand-ecc-opts= | | | OMAP_ECC_BCH8_CODE_HW | "bch8" | |(8-bit BCH | #define CONFIG_SYS_NAND_ECCBYTES 14 | | | using ELM | #define CONFIG_SPL_NAND_AM33XX_BCH |(with ELM node) | | h/w engine | #define CONFIG_SYS_NAND_ECCPOS \ |ti,elm-id=<&elm> | |for ECC | {2, 3, 4, 5, 6, 7, 8, 9, \ | | | error | 10, 11, 12, 13, 14, 15, 16, 17, \ | | |correction) | 18, 19, 20, 21, 22, 23, 24, 25, \ | | | | 26, 27, 28, 29, 30, 31, 32, 33, \ | | | | 34, 35, 36, 37, 38, 39, 40, 41, \ | | | | 42, 43, 44, 45, 46, 47, 48, 49, \ | | | | 50, 51, 52, 53, 54, 55, 56, 57, } | | | | (for NAND page-size=2048) | | | | #define CONFIG_SYS_NAND_ECCSIZE 512 | | | | | | +------------+--------------------------------------------+------------------+ Test1: flash ubi image from u-boot and boot the kernel U-boot> mw 0x82000000 0xff U-boot> fatload mmc 0 0x82000000 u-boot.img U-boot> nand erase U-boot> nand write 0x82000000 U-boot> setenv bootargs 'console=ttyO0,115200n8 noinitrd mem=256M \ root=ubi0 rw rootfstype=ubifs ubi.mtd=,\ ip=off init=/init' U-boot> bootm Test2: update u-boot.img from kernel and re-boot Kernel> flash_erase /dev/ 0 0 Kernel> nandwrite -s 0 /dev/ u-boot.img Kernel> reboot Signed-off-by: Pekon Gupta --- drivers/mtd/nand/omap2.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index bbdb5e8..e7836bf 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -1633,6 +1633,7 @@ static int omap_nand_probe(struct platform_device *pdev) int i; dma_cap_mask_t mask; unsigned sig; + unsigned oob_index; struct resource *res; struct mtd_part_parser_data ppdata = {}; @@ -1832,9 +1833,11 @@ static int omap_nand_probe(struct platform_device *pdev) (mtd->writesize / nand_chip->ecc.size); if (nand_chip->options & NAND_BUSWIDTH_16) - ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; + oob_index = BADBLOCK_MARKER_LENGTH; else - ecclayout->eccpos[0] = 1; + oob_index = 1; + for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) + ecclayout->eccpos[i] = oob_index; break; case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: @@ -1851,7 +1854,13 @@ static int omap_nand_probe(struct platform_device *pdev) ecclayout->eccbytes = nand_chip->ecc.bytes * (mtd->writesize / nand_chip->ecc.size); - ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; + oob_index = BADBLOCK_MARKER_LENGTH; + for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) { + if ((i % nand_chip->ecc.bytes) || (i == 0)) + ecclayout->eccpos[i] = oob_index; + else + ecclayout->eccpos[i] = ++oob_index; + } /* software bch library is used for locating errors */ nand_chip->ecc.priv = nand_bch_init(mtd, nand_chip->ecc.size, @@ -1885,7 +1894,9 @@ static int omap_nand_probe(struct platform_device *pdev) ecclayout->eccbytes = nand_chip->ecc.bytes * (mtd->writesize / nand_chip->ecc.size); - ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; + oob_index = BADBLOCK_MARKER_LENGTH; + for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) + ecclayout->eccpos[i] = oob_index; /* This ECC scheme requires ELM H/W block */ if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) { pr_err("nand: error: could not initialize ELM\n"); @@ -1913,7 +1924,13 @@ static int omap_nand_probe(struct platform_device *pdev) ecclayout->eccbytes = nand_chip->ecc.bytes * (mtd->writesize / nand_chip->ecc.size); - ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; + oob_index = BADBLOCK_MARKER_LENGTH; + for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) { + if ((i % nand_chip->ecc.bytes) || (i == 0)) + ecclayout->eccpos[i] = oob_index; + else + ecclayout->eccpos[i] = ++oob_index; + } /* software bch library is used for locating errors */ nand_chip->ecc.priv = nand_bch_init(mtd, nand_chip->ecc.size, @@ -1954,7 +1971,9 @@ static int omap_nand_probe(struct platform_device *pdev) ecclayout->eccbytes = nand_chip->ecc.bytes * (mtd->writesize / nand_chip->ecc.size); - ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; + oob_index = BADBLOCK_MARKER_LENGTH; + for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) + ecclayout->eccpos[i] = oob_index; break; #else pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); @@ -1968,8 +1987,6 @@ static int omap_nand_probe(struct platform_device *pdev) goto return_error; } - for (i = 1; i < ecclayout->eccbytes; i++) - ecclayout->eccpos[i] = ecclayout->eccpos[0] + i; /* check if NAND device's OOB is enough to store ECC signatures */ if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) { pr_err("not enough OOB bytes required = %d, available=%d\n",