From patchwork Thu Dec 19 11:23:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 3376861 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8312CC0D4A for ; Thu, 19 Dec 2013 11:25:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E13CA20627 for ; Thu, 19 Dec 2013 11:25:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 300202063B for ; Thu, 19 Dec 2013 11:25:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753443Ab3LSLZ2 (ORCPT ); Thu, 19 Dec 2013 06:25:28 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:42450 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753427Ab3LSLZ1 (ORCPT ); Thu, 19 Dec 2013 06:25:27 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id rBJBP2VM004932; Thu, 19 Dec 2013 05:25:02 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id rBJBP1Ig029551; Thu, 19 Dec 2013 05:25:02 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Thu, 19 Dec 2013 05:25:01 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id rBJBOUh3009888; Thu, 19 Dec 2013 05:24:59 -0600 From: Tero Kristo To: , , , , , , CC: , Subject: [PATCHv11 09/49] clk: mux: add support for low level ops Date: Thu, 19 Dec 2013 13:23:40 +0200 Message-ID: <1387452260-23276-10-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1387452260-23276-1-git-send-email-t-kristo@ti.com> References: <1387452260-23276-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Multiplexer clock can now be registered to use low level register access ops. Preferred initialization method is via clock description. Signed-off-by: Tero Kristo --- drivers/clk/clk-mux.c | 11 ++++++++--- include/linux/clk-provider.h | 4 ++++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 2cbed08..1a603f3 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -46,7 +46,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so * val = 0x4 really means "bit 2, index starts at bit 0" */ - val = clk_readl(mux->reg) >> mux->shift; + val = mux->ll_ops->clk_readl(mux->reg) >> mux->shift; val &= mux->mask; if (mux->table) { @@ -93,11 +93,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) if (mux->flags & CLK_MUX_HIWORD_MASK) { val = mux->mask << (mux->shift + 16); } else { - val = clk_readl(mux->reg); + val = mux->ll_ops->clk_readl(mux->reg); val &= ~(mux->mask << mux->shift); } val |= index << mux->shift; - clk_writel(val, mux->reg); + mux->ll_ops->clk_writel(val, mux->reg); if (mux->lock) spin_unlock_irqrestore(mux->lock, flags); @@ -159,6 +159,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, mux->lock = lock; mux->table = table; mux->hw.init = &init; + mux->ll_ops = &clk_ll_ops_default; clk = clk_register(dev, &mux->hw); @@ -201,6 +202,10 @@ struct clk_hw *clk_register_mux_desc(struct device *dev, struct clk_desc *desc) mux->shift = hw_desc->shift; mux->flags = hw_desc->flags; mux->lock = hw_desc->lock; + mux->ll_ops = hw_desc->ll_ops; + + if (!mux->ll_ops) + mux->ll_ops = &clk_ll_ops_default; if (!desc->ops) { if (mux->flags & CLK_MUX_READ_ONLY) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 0bbf231..8b46a7b 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -407,6 +407,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling multiplexer + * @ll_ops: low-level ops for accessing the register * @shift: shift to multiplexer bit field * @width: width of mutliplexer bit field * @flags: hardware-specific flags @@ -426,6 +427,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, struct clk_mux { struct clk_hw hw; void __iomem *reg; + struct clk_ll_ops *ll_ops; u32 *table; u32 mask; u8 shift; @@ -438,6 +440,7 @@ struct clk_mux { * * @desc: handle between common and hardware-specific interfaces * @reg: register controlling multiplexer + * @ll_ops: low-level ops for accesing the register * @shift: shift to multiplexer bit field * @width: width of multiplexer bit field * @flags: hardware-specific flags @@ -446,6 +449,7 @@ struct clk_mux { struct clk_mux_desc { struct clk_desc desc; void __iomem *reg; + struct clk_ll_ops *ll_ops; u32 *table; u32 mask; u8 shift;