From patchwork Thu Jan 9 14:00:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 3460751 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CF7DD9F1C4 for ; Thu, 9 Jan 2014 14:04:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B8F5520127 for ; Thu, 9 Jan 2014 14:04:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9EC2B2012F for ; Thu, 9 Jan 2014 14:04:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756540AbaAIOEd (ORCPT ); Thu, 9 Jan 2014 09:04:33 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:46980 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756284AbaAIODr (ORCPT ); Thu, 9 Jan 2014 09:03:47 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s09E2usm021452; Thu, 9 Jan 2014 08:02:56 -0600 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s09E2u3Z028962; Thu, 9 Jan 2014 08:02:56 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Thu, 9 Jan 2014 08:02:55 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s09E12Wc030058; Thu, 9 Jan 2014 08:02:53 -0600 From: Tero Kristo To: , , , , , , CC: , Subject: [PATCHv13 34/40] ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT Date: Thu, 9 Jan 2014 16:00:45 +0200 Message-ID: <1389276051-1326-35-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1389276051-1326-1-git-send-email-t-kristo@ti.com> References: <1389276051-1326-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch provides top level functionality for the DT clock initialization. Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM) going down towards individual clock nodes, and finally initializing clockdomains once all the clocks are ready. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/prm.h | 1 + arch/arm/mach-omap2/prm_common.c | 66 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index ac25ae6..623db40 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -18,6 +18,7 @@ # ifndef __ASSEMBLER__ extern void __iomem *prm_base; extern void omap2_set_globals_prm(void __iomem *prm); +int of_prcm_init(void); # endif diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index a2e1174..b4c4ab9 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -23,6 +23,10 @@ #include #include #include +#include +#include +#include +#include #include "soc.h" #include "prm2xxx_3xxx.h" @@ -30,6 +34,7 @@ #include "prm3xxx.h" #include "prm44xx.h" #include "common.h" +#include "clock.h" /* * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs @@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld) return 0; } + +static struct of_device_id omap_prcm_dt_match_table[] = { + { .compatible = "ti,am3-prcm" }, + { .compatible = "ti,am3-scrm" }, + { .compatible = "ti,am4-prcm" }, + { .compatible = "ti,am4-scrm" }, + { .compatible = "ti,omap3-prm" }, + { .compatible = "ti,omap3-cm" }, + { .compatible = "ti,omap3-scrm" }, + { .compatible = "ti,omap4-cm1" }, + { .compatible = "ti,omap4-prm" }, + { .compatible = "ti,omap4-cm2" }, + { .compatible = "ti,omap4-scrm" }, + { .compatible = "ti,omap5-prm" }, + { .compatible = "ti,omap5-cm-core-aon" }, + { .compatible = "ti,omap5-scrm" }, + { .compatible = "ti,omap5-cm-core" }, + { .compatible = "ti,dra7-prm" }, + { .compatible = "ti,dra7-cm-core-aon" }, + { .compatible = "ti,dra7-cm-core" }, + { } +}; + +static struct clk_hw_omap memmap_dummy_ck = { + .flags = MEMMAP_ADDRESSING, +}; + +static u32 prm_clk_readl(void __iomem *reg) +{ + return omap2_clk_readl(&memmap_dummy_ck, reg); +} + +static void prm_clk_writel(u32 val, void __iomem *reg) +{ + omap2_clk_writel(val, &memmap_dummy_ck, reg); +} + +static struct ti_clk_ll_ops omap_clk_ll_ops = { + .clk_readl = prm_clk_readl, + .clk_writel = prm_clk_writel, +}; + +int __init of_prcm_init(void) +{ + struct device_node *np; + void __iomem *mem; + int memmap_index = 0; + + ti_clk_ll_ops = &omap_clk_ll_ops; + + for_each_matching_node(np, omap_prcm_dt_match_table) { + mem = of_iomap(np, 0); + clk_memmaps[memmap_index] = mem; + ti_dt_clk_init_provider(np, memmap_index); + memmap_index++; + } + + ti_dt_clockdomains_setup(); + + return 0; +}