From patchwork Fri Mar 7 13:24:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 3791301 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1F8C6BF540 for ; Fri, 7 Mar 2014 13:26:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1F52D20122 for ; Fri, 7 Mar 2014 13:26:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 01FA1202B8 for ; Fri, 7 Mar 2014 13:26:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753263AbaCGN0e (ORCPT ); Fri, 7 Mar 2014 08:26:34 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:46965 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752533AbaCGN0d (ORCPT ); Fri, 7 Mar 2014 08:26:33 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s27DQ41V004921; Fri, 7 Mar 2014 07:26:04 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s27DQ4D1031450; Fri, 7 Mar 2014 07:26:04 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Fri, 7 Mar 2014 07:26:03 -0600 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s27DPkfa022073; Fri, 7 Mar 2014 07:26:00 -0600 From: Pekon Gupta To: Brian Norris , Tony Lindgren CC: linux-mtd , Ezequiel Garcia , Stefan Roese , Jon Cormier , Daniel Mack , Felipe Balbi , linux-omap , Pekon Gupta Subject: [PATCH v2 4/4] mtd: nand: omap: Documentation: How to select correct ECC scheme for your device ? Date: Fri, 7 Mar 2014 18:54:53 +0530 Message-ID: <1394198693-8003-5-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.5.1.163.gd7aced9 In-Reply-To: <1394198693-8003-1-git-send-email-pekon@ti.com> References: <1394198693-8003-1-git-send-email-pekon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - Adds DT binding property for BCH16 ECC scheme - Adds describes on factors which determine choice of ECC scheme for particular device Signed-off-by: Pekon Gupta --- .../devicetree/bindings/mtd/gpmc-nand.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt index 5e1f31b..f2dbb33 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt @@ -28,6 +28,8 @@ Optional properties: "ham1" 1-bit Hamming ecc code "bch4" 4-bit BCH ecc code "bch8" 8-bit BCH ecc code + "bch16" 16-bit BCH ECC code + Refer below "How to select correct ECC scheme for your device ?" - ti,nand-xfer-type: A string setting the data transfer type. One of: @@ -90,3 +92,40 @@ Example for an AM33xx board: }; }; +How to select correct ECC scheme for your device ? +-------------------------------------------------- +Higher ECC scheme usually means better protection against bit-flips and +increased system lifetime. However, selection of ECC scheme is dependent +on various other factors like; +(1) Presence of supporting hardware engines on SoC. + Some legacy OMAP SoC do not have ELM h/w engine thus such SoC cannot + support BCHx_HW ECC schemes. But such SoC can support + BCHx_HW_DETECTION_SW ECC schemes which use s/w library with slight + CPU performance panalty only when too bit-flips are detected. +(2) Device parameters like OOBSIZE + Higher ECC schemes require more OOB/Spare area to store ECC. + So choice of ECC scheme is limited by NAND oobsize. In general + following expression help determine whether given device can + accomodate ECC syndrome or not: + "2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE + where + OOBSIZE number of bytes in OOB/spare area + PAGESIZE number of bytes in main-area of device page + ECC_BYTES number of ECC bytes generated to protect + 512 bytes of data, which is: + '3' for HAM1_xx ecc schemes + '7' for BCH4_xx ecc schemes + '14' for BCH8_xx ecc schemes + '26' for BCH16_xx ecc schemes + + Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 + Number of spare/OOB bytes required for using BCH16 ecc-scheme + "(2 + (2048 / 512) * 26) = 106 bytes" is greater than OOBSIZE + (As per above table for BCH16 ecc-scheme, ECC_BYTES = 26) + Thus BCH16 cannot be supported on 2K NAND with OOBSIZE=64 bytes + + Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 + Number of spare/OOB bytes required for using BCH16 ecc-scheme + "(2 + (2048 / 512) * 26) = 106 bytes" is less than OOBSIZE + (As per above table for BCH16 ecc-scheme, ECC_BYTES = 26) + Thus BCH16 can be supported on 4K NAND with OOBSIZE=128 bytes