From patchwork Sat Mar 29 00:31:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 3907951 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6B4A39F2E8 for ; Sat, 29 Mar 2014 00:35:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 803432035D for ; Sat, 29 Mar 2014 00:35:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8C80520351 for ; Sat, 29 Mar 2014 00:35:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752245AbaC2Ael (ORCPT ); Fri, 28 Mar 2014 20:34:41 -0400 Received: from ring0.de ([5.45.105.125]:43186 "EHLO ring0.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751494AbaC2Aej (ORCPT ); Fri, 28 Mar 2014 20:34:39 -0400 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 From: Sebastian Reichel To: Sebastian Reichel , Linus Walleij , Shubhrajyoti Datta , Carlos Chinea Cc: Tony Lindgren , Rob Herring , Pawel Moll , Mark Rutland , Kumar Gala , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, =?UTF-8?q?Pali=20Roh=C3=A1r?= , =?UTF-8?q?=D0=98=D0=B2=D0=B0=D0=B9=D0=BB=D0=BE=20=D0=94=D0=B8=D0=BC=D0=B8=D1=82=D1=80=D0=BE=D0=B2?= , Joni Lapilainen , Aaro Koskinen , Sebastian Reichel Subject: [PATCHv3 12/14] ARM: dts: omap3 clocks: simplify ssi aliases Date: Sat, 29 Mar 2014 01:31:48 +0100 Message-Id: <1396053110-21639-13-git-send-email-sre@kernel.org> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1396053110-21639-1-git-send-email-sre@kernel.org> References: <1396053110-21639-1-git-send-email-sre@kernel.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sebastian Reichel update aliases for the ssi clocks ssi_ssr_fck, ssi_sst_fck and ssi_ick to make them consistent for omap34xx and omap36xx. This makes it possible to reference the clocks from generic omap3 dts files. Signed-off-by: Sebastian Reichel Acked-by: Tero Kristo Reviewed-by: Pavel Machek --- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 10 +++++----- arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 02f6c7f..6f31954 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -82,16 +82,16 @@ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; }; - ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 { + ssi_ssr_fck: ssi_ssr_fck_3430es1 { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; }; - ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 { + ssi_sst_fck: ssi_sst_fck_3430es1 { #clock-cells = <0>; compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck_3430es1>; + clocks = <&ssi_ssr_fck>; clock-mult = <1>; clock-div = <2>; }; @@ -120,7 +120,7 @@ clock-div = <1>; }; - ssi_ick_3430es1: ssi_ick_3430es1 { + ssi_ick: ssi_ick_3430es1 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&ssi_l4_ick>; @@ -203,6 +203,6 @@ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>; + <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; }; }; diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 8ed475d..877318c 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -25,16 +25,16 @@ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; }; - ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 { + ssi_ssr_fck: ssi_ssr_fck_3430es2 { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; }; - ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 { + ssi_sst_fck: ssi_sst_fck_3430es2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck_3430es2>; + clocks = <&ssi_ssr_fck>; clock-mult = <1>; clock-div = <2>; }; @@ -55,7 +55,7 @@ clock-div = <1>; }; - ssi_ick_3430es2: ssi_ick_3430es2 { + ssi_ick: ssi_ick_3430es2 { #clock-cells = <0>; compatible = "ti,omap3-ssi-interface-clock"; clocks = <&ssi_l4_ick>; @@ -193,6 +193,6 @@ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&ssi_ick_3430es2>; + <&ssi_ick>; }; };