From patchwork Mon Mar 31 15:16:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 3915821 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D802A9F357 for ; Mon, 31 Mar 2014 15:18:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 003072039C for ; Mon, 31 Mar 2014 15:18:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0905820204 for ; Mon, 31 Mar 2014 15:18:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753954AbaCaPSu (ORCPT ); Mon, 31 Mar 2014 11:18:50 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:58861 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753924AbaCaPSs (ORCPT ); Mon, 31 Mar 2014 11:18:48 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s2VFIFrC022481; Mon, 31 Mar 2014 10:18:15 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2VFIFNJ024021; Mon, 31 Mar 2014 10:18:15 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Mon, 31 Mar 2014 10:18:15 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2VFGm4Q013169; Mon, 31 Mar 2014 10:18:11 -0500 From: Tero Kristo To: , , CC: Subject: [PATCH 39/55] ARM: OMAP5: PRM: remove direct register declaration macros Date: Mon, 31 Mar 2014 18:16:18 +0300 Message-ID: <1396278994-12624-40-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1396278994-12624-1-git-send-email-t-kristo@ti.com> References: <1396278994-12624-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP None of these are currently used, so cleanup. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/prm54xx.h | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h index e441101..3f1b383 100644 --- a/arch/arm/mach-omap2/prm54xx.h +++ b/arch/arm/mach-omap2/prm54xx.h @@ -69,7 +69,6 @@ #define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030 #define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038 #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040) #define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084 #define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090 #define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094 @@ -80,13 +79,9 @@ /* PRM.CKGEN_PRM register offsets */ #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000 -#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000) #define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 -#define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008) #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c -#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c) #define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010 -#define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010) /* PRM.MPU_PRM register offsets */ #define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 @@ -314,27 +309,16 @@ /* PRM.WKUPAON_CM register offsets */ #define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020) #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028) #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 -#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030) #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 -#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038) #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 -#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040) #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 -#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048) #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 -#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050) #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 -#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060) #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 -#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078) #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 -#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090) #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 -#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098) /* PRM.EMU_PRM register offsets */ #define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 @@ -345,9 +329,7 @@ #define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 #define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020) #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028) /* PRM.DEVICE_PRM register offsets */ #define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000