From patchwork Wed Jul 9 12:21:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rostislav Lisovy X-Patchwork-Id: 4514561 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 68A40BEEAA for ; Wed, 9 Jul 2014 12:21:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 67E742034F for ; Wed, 9 Jul 2014 12:21:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3B2092015E for ; Wed, 9 Jul 2014 12:21:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755661AbaGIMVi (ORCPT ); Wed, 9 Jul 2014 08:21:38 -0400 Received: from mail-wg0-f43.google.com ([74.125.82.43]:50547 "EHLO mail-wg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753507AbaGIMVh (ORCPT ); Wed, 9 Jul 2014 08:21:37 -0400 Received: by mail-wg0-f43.google.com with SMTP id b13so7279375wgh.26 for ; Wed, 09 Jul 2014 05:21:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=R9HzhoJcSrhCsz8LOzKz+ELIgXysWJ2iyqLLu0yHTFY=; b=oCEyM2sv5ZEVqcqQleHEZym9u6dl8kxCjFZOsB1CggvJQoUsyRXhBEGiGWGirTD8ln rHF/HdnsdIzC43qyMu1/+Cpv56ytaQLyyrLsYoZnpC/T0+lnuDeaih7LhxA6q/Q+GEXx oC4phTWJX95gZkv1nDz2ChRdig9e5nfqZeeJltldOcmTcq2yRQD0n36FMsDnCnU96dkz +sbrnnNeJKN5GyzKcAlcaNCNPhDRWXkRwpxr5ZWNXWziuOnKzaFpWDr3lxYu95pBR31K bBas8Ebhe/sy1sFVWeoAmu/F8BbmIVIR6lGlHpOoJs/h/b1p3F0a0LTdstBz6jsuMdZl VopQ== X-Received: by 10.194.89.168 with SMTP id bp8mr48303016wjb.73.1404908496289; Wed, 09 Jul 2014 05:21:36 -0700 (PDT) Received: from lp-lvrv.comap.cz ([195.122.193.158]) by mx.google.com with ESMTPSA id q11sm18845797wib.14.2014.07.09.05.21.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Jul 2014 05:21:35 -0700 (PDT) From: Rostislav Lisovy X-Google-Original-From: Rostislav Lisovy To: Tony Lindgren , Pekon Gupta , linux-omap@vger.kernel.org Cc: Kevin Hilman , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Michal Vokac , Michal Sojka , lisovy@gmail.com, Rostislav Lisovy Subject: [PATCH RESEND] ARM: omap2+: gpmc-nand: Use dynamic platform_device_alloc() Date: Wed, 9 Jul 2014 14:21:19 +0200 Message-Id: <1404908479-11196-1-git-send-email-lisovy@merica.cz> X-Mailer: git-send-email 1.9.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP GPMC controller supports up to 8 memory devices connected to it. Since there is one statically allocated "struct platform_device gpmc_nand_device" it is not possible to configure the system to use more than one NAND device connected to the GPMC. This modification makes it possible to use up to 8 NAND devices connected to the GPMC controller. Signed-off-by: Rostislav Lisovy --- Tested on custom AM335x board with two different NAND chips (128 + 256 MiB) using GPMC configuration in FDT -- behaves correctly. arch/arm/mach-omap2/gpmc-nand.c | 79 +++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 42 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 4349e82..c5481a8 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -24,25 +24,6 @@ /* minimum size for IO mapping */ #define NAND_IO_SIZE 4 -static struct resource gpmc_nand_resource[] = { - { - .flags = IORESOURCE_MEM, - }, - { - .flags = IORESOURCE_IRQ, - }, - { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device gpmc_nand_device = { - .name = "omap2-nand", - .id = 0, - .num_resources = ARRAY_SIZE(gpmc_nand_resource), - .resource = gpmc_nand_resource, -}; - static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* platforms which support all ECC schemes */ @@ -93,43 +74,41 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, { int err = 0; struct gpmc_settings s; - struct device *dev = &gpmc_nand_device.dev; - - memset(&s, 0, sizeof(struct gpmc_settings)); + struct platform_device *pdev; + struct resource gpmc_nand_res[] = { + { .flags = IORESOURCE_MEM, }, + { .flags = IORESOURCE_IRQ, }, + { .flags = IORESOURCE_IRQ, }, + }; - gpmc_nand_device.dev.platform_data = gpmc_nand_data; + BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM); err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, - (unsigned long *)&gpmc_nand_resource[0].start); + (unsigned long *)&gpmc_nand_res[0].start); if (err < 0) { - dev_err(dev, "Cannot request GPMC CS %d, error %d\n", - gpmc_nand_data->cs, err); + pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n", + gpmc_nand_data->cs, err); return err; } - - gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + - NAND_IO_SIZE - 1; - - gpmc_nand_resource[1].start = - gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); - gpmc_nand_resource[2].start = - gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); + gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1; + gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); + gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); if (gpmc_t) { err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); if (err < 0) { - dev_err(dev, "Unable to set gpmc timings: %d\n", err); + pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err); return err; } } + memset(&s, 0, sizeof(struct gpmc_settings)); if (gpmc_nand_data->of_node) gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); else gpmc_set_legacy(gpmc_nand_data, &s); s.device_nand = true; - err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); if (err < 0) goto out_free_cs; @@ -141,18 +120,34 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { - dev_err(dev, "Unsupported NAND ECC scheme selected\n"); - return -EINVAL; + pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n"); + err = -EINVAL; + goto out_free_cs; } - err = platform_device_register(&gpmc_nand_device); - if (err < 0) { - dev_err(dev, "Unable to register NAND device\n"); - goto out_free_cs; + + pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs); + if (pdev) { + err = platform_device_add_resources(pdev, gpmc_nand_res, + ARRAY_SIZE(gpmc_nand_res)); + if (!err) + pdev->dev.platform_data = gpmc_nand_data; + } else { + err = -ENOMEM; + } + if (err) + goto out_free_pdev; + + err = platform_device_add(pdev); + if (err) { + dev_err(&pdev->dev, "Unable to register NAND device\n"); + goto out_free_pdev; } return 0; +out_free_pdev: + platform_device_put(pdev); out_free_cs: gpmc_cs_free(gpmc_nand_data->cs);