From patchwork Fri Jul 11 02:55:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 4529611 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4988EBEEAA for ; Fri, 11 Jul 2014 02:57:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 76D2F201F5 for ; Fri, 11 Jul 2014 02:57:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 914BB201F2 for ; Fri, 11 Jul 2014 02:57:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751943AbaGKC5c (ORCPT ); Thu, 10 Jul 2014 22:57:32 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:35339 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751734AbaGKC5b (ORCPT ); Thu, 10 Jul 2014 22:57:31 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6B2v7IV015036; Thu, 10 Jul 2014 21:57:07 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6B2v7NE024788; Thu, 10 Jul 2014 21:57:07 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Thu, 10 Jul 2014 21:57:07 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6B2v7Qb032595; Thu, 10 Jul 2014 21:57:07 -0500 Received: from localhost (j-172-22-132-241.vpn.ti.com [172.22.132.241]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s6B2v6t15871; Thu, 10 Jul 2014 21:57:06 -0500 (CDT) From: Dave Gerlach To: , CC: Paul Walmsley , Kevin Hilman , Tony Lindgren , Tero Kristo , Nishanth Menon , Russ Dill , Santosh Shilimkar , Daniel Mack , Suman Anna , Benoit Cousson , Vaibhav Bedia , Dave Gerlach Subject: [PATCH v4 03/11] ARM: OMAP2+: timer: Add suspend-resume callbacks for clkevent device Date: Thu, 10 Jul 2014 21:55:41 -0500 Message-ID: <1405047349-15101-4-git-send-email-d-gerlach@ti.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1405047349-15101-1-git-send-email-d-gerlach@ti.com> References: <1405047349-15101-1-git-send-email-d-gerlach@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vaibhav Bedia OMAP timer code registers two timers - one as clocksource and one as clockevent. Since AM33XX has only one usable timer in the WKUP domain one of the timers needs suspend-resume support to restore the configuration to pre-suspend state. commit adc78e6 (timekeeping: Add suspend and resume of clock event devices) introduced .suspend and .resume callbacks for clock event devices. Leverages these callbacks to have AM33XX clockevent timer which is in not in WKUP domain to behave properly across system suspend. Signed-off-by: Vaibhav Bedia Signed-off-by: Dave Gerlach --- v3->v4: Only use for am33xx soc now. arch/arm/mach-omap2/timer.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 43d03fb..6fc1748 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -128,6 +128,29 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, } } +static void omap_clkevt_suspend(struct clock_event_device *unused) +{ + struct omap_hwmod *oh; + + oh = omap_hwmod_lookup(clockevent_gpt.name); + if (!oh) + return; + + omap_hwmod_idle(oh); +} + +static void omap_clkevt_resume(struct clock_event_device *unused) +{ + struct omap_hwmod *oh; + + oh = omap_hwmod_lookup(clockevent_gpt.name); + if (!oh) + return; + + omap_hwmod_enable(oh); + __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); +} + static struct clock_event_device clockevent_gpt = { .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .rating = 300, @@ -333,6 +356,11 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, clkev.id = gptimer_id; clkev.errata = omap_dm_timer_get_errata(); + if (soc_is_am33xx()) { + clockevent_gpt.suspend = omap_clkevt_suspend; + clockevent_gpt.resume = omap_clkevt_resume; + } + /* * For clock-event timers we never read the timer counter and * so we are not impacted by errata i103 and i767. Therefore,