From patchwork Wed Jul 23 18:17:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 4612551 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4448EC0514 for ; Wed, 23 Jul 2014 18:17:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6D4D3201DD for ; Wed, 23 Jul 2014 18:17:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B2DE0201DC for ; Wed, 23 Jul 2014 18:17:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932561AbaGWSRx (ORCPT ); Wed, 23 Jul 2014 14:17:53 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:37723 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932503AbaGWSRw (ORCPT ); Wed, 23 Jul 2014 14:17:52 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6NIHl4T023225; Wed, 23 Jul 2014 13:17:47 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6NIHlqE021539; Wed, 23 Jul 2014 13:17:47 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 23 Jul 2014 13:17:47 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6NIHjZs020347; Wed, 23 Jul 2014 13:17:45 -0500 From: Pekon Gupta To: Tony Lindgren CC: linux-omap , Roger Quadros , Javier Martinez Canillas , Pekon Gupta Subject: [PATCH] ARM: OMAP2+: fix gpmc_cs_remap: re-allocating chip-select address space based on DT Date: Wed, 23 Jul 2014 23:47:38 +0530 Message-ID: <1406139458-11676-1-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.5.1.163.gd7aced9 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Each GPMC chip-select needs to be configured for (base-address,CS-size) so that GPMC understands the address-space allocated to device connected externally. These chip-select configurations (base-address, CS-size) follow some basic mapping rules like: - The CS size is programmable from 256 MBytes to 16 MBytes (must be a power of 2) and is defined by the mask field. Attached memory smaller than the programmed CS region size is accessed through the entire CS region (aliasing). - The programmed 'base-address' must be aligned to the 'CS-size' boundary and be a power of 2. - Valid CS-size values are {256MB(max), 128MB, 64MB, 32MB and 16MB (min)} Any intermediate values creates holes in the chip-select memory-map. This patch adds above checks in gpmc_cs_remap() so that any invalid value passed by DT property can be filtered before actually allocating the address space. Signed-off-by: Pekon Gupta --- arch/arm/mach-omap2/gpmc.c | 42 +++++++++++++++++++++++++++++------------- 1 file changed, 29 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 8bc1338..4a4cc04 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -521,26 +521,42 @@ static int gpmc_cs_delete_mem(int cs) * "base". Returns 0 on success and appropriate negative error code * on failure. */ -static int gpmc_cs_remap(int cs, u32 base) +static int gpmc_cs_remap(int cs, u32 base, u32 size) { int ret; - u32 old_base, size; if (cs > gpmc_cs_num) { pr_err("%s: requested chip-select is disabled\n", __func__); return -ENODEV; } - /* - * Make sure we ignore any device offsets from the GPMC partition - * allocated for the chip select and that the new base confirms - * to the GPMC 16MB minimum granularity. - */ - base &= ~(SZ_16M - 1); - - gpmc_cs_get_memconf(cs, &old_base, &size); - if (base == old_base) - return 0; + /* allocate enough address-space under GPMC chip-select to device */ + if (size > SZ_256M) { + pr_err("%s: memory device > 256MB not supported\n", __func__); + return -ENODEV; + } else if (size > SZ_128M) { + WARN((size != SZ_256M), "cs=%d: allocating 256MB\n", cs); + size = SZ_256M; + } else if (size > SZ_64M) { + WARN((size != SZ_128M), "cs=%d: allocating 128MB\n", cs); + size = SZ_128M; + } else if (size > SZ_32M) { + WARN((size != SZ_64M), "cs=%d: allocating 64MB\n", cs); + size = SZ_64M; + } else if (size > SZ_16M) { + WARN((size != SZ_32M), "cs=%d: allocating 64MB\n", cs); + size = SZ_32M; + } else { + WARN((size != SZ_16M), "cs=%d: allocating 64MB\n", cs); + size = SZ_16M; + } + + /* base address should be aligned with address-space size */ + if (base & (size - 1)) { + pr_err("base-addr=%x should be aligned to size=%x", base, size); + return -EINVAL; + } + gpmc_cs_disable_mem(cs); ret = gpmc_cs_delete_mem(cs); if (ret < 0) @@ -1551,7 +1567,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, * CS to this location. Once DT migration is complete should * just make gpmc_cs_request() map a specific address. */ - ret = gpmc_cs_remap(cs, res.start); + ret = gpmc_cs_remap(cs, res.start, resource_size(&res)); if (ret < 0) { dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", cs, &res.start);