From patchwork Wed Oct 22 08:39:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 5130351 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7A1009F30B for ; Wed, 22 Oct 2014 08:40:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 06B8C201FE for ; Wed, 22 Oct 2014 08:40:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0FBAE201F4 for ; Wed, 22 Oct 2014 08:40:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753961AbaJVIkJ (ORCPT ); Wed, 22 Oct 2014 04:40:09 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:39924 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753677AbaJVIkH (ORCPT ); Wed, 22 Oct 2014 04:40:07 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s9M8e6J6002597; Wed, 22 Oct 2014 03:40:06 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9M8e6TR022140; Wed, 22 Oct 2014 03:40:06 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 22 Oct 2014 03:40:05 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9M8e4Vq011501; Wed, 22 Oct 2014 03:40:05 -0500 From: Tomi Valkeinen To: , CC: Tomi Valkeinen Subject: [PATCH 1/5] OMAPDSS: HDMI: fix PLL GO bit handling Date: Wed, 22 Oct 2014 11:39:30 +0300 Message-ID: <1413967174-28009-1-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.1.1 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PLL settings are committed by setting GO bit, which is then cleared by the HW when the settings have been taken into use. The current PLL code handles this wrong: instead of waiting for the bit to be cleared, it waits for the bit to be set. Usually, the bit is always set, as the CPU has just set it before. However, if the CPU takes enough time between setting the GO bit and checking it, the HW may already have cleared the bit and this leads to timeout error. Fix the wait to check the bit properly. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/hdmi_pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/fbdev/omap2/dss/hdmi_pll.c b/drivers/video/fbdev/omap2/dss/hdmi_pll.c index 54df12a8d744..d4ec815ba42e 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_pll.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_pll.c @@ -144,8 +144,8 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll) /* wait for bit change */ if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO, - 0, 0, 1) != 1) { - DSSERR("PLL GO bit not set\n"); + 0, 0, 0) != 0) { + DSSERR("PLL GO bit not clearing\n"); return -ETIMEDOUT; }