From patchwork Wed Oct 22 08:39:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 5130371 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C7CEAC11AD for ; Wed, 22 Oct 2014 08:40:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 09F9C201CE for ; Wed, 22 Oct 2014 08:40:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1B361201FB for ; Wed, 22 Oct 2014 08:40:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754016AbaJVIkL (ORCPT ); Wed, 22 Oct 2014 04:40:11 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:43580 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751296AbaJVIkI (ORCPT ); Wed, 22 Oct 2014 04:40:08 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s9M8e7Hx021695; Wed, 22 Oct 2014 03:40:07 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9M8e7xK024092; Wed, 22 Oct 2014 03:40:07 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 22 Oct 2014 03:40:07 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9M8e4Vr011501; Wed, 22 Oct 2014 03:40:06 -0500 From: Tomi Valkeinen To: , CC: Tomi Valkeinen Subject: [PATCH 2/5] OMAPDSS: HDMI: fix regsd write Date: Wed, 22 Oct 2014 11:39:31 +0300 Message-ID: <1413967174-28009-2-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1413967174-28009-1-git-send-email-tomi.valkeinen@ti.com> References: <1413967174-28009-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP HDMI PLL's REGSD field is only set by the driver if the PLL's output clock is over 1GHz. This is clearly an error, as REGSD should be set always. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/hdmi_pll.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/video/fbdev/omap2/dss/hdmi_pll.c b/drivers/video/fbdev/omap2/dss/hdmi_pll.c index d4ec815ba42e..6d92bb32fe51 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_pll.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_pll.c @@ -124,16 +124,15 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll) r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */ - if (fmt->dcofreq) { - /* divider programming for frequency beyond 1000Mhz */ - REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10); + if (fmt->dcofreq) r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ - } else { + else r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ - } hdmi_write_reg(pll->base, PLLCTRL_CFG2, r); + REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10); + r = hdmi_read_reg(pll->base, PLLCTRL_CFG4); r = FLD_MOD(r, fmt->regm2, 24, 18); r = FLD_MOD(r, fmt->regmf, 17, 0);