From patchwork Wed Oct 29 09:23:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 5185651 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A9267C11AC for ; Wed, 29 Oct 2014 09:24:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EA961201DD for ; Wed, 29 Oct 2014 09:24:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AE9AC2021A for ; Wed, 29 Oct 2014 09:24:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756497AbaJ2JXx (ORCPT ); Wed, 29 Oct 2014 05:23:53 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:62599 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756404AbaJ2JXU (ORCPT ); Wed, 29 Oct 2014 05:23:20 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NE70095H8VH8A60@mailout3.w1.samsung.com>; Wed, 29 Oct 2014 09:26:05 +0000 (GMT) X-AuditID: cbfec7f4-b7f6c6d00000120b-f1-5450b2019e2c Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id CD.04.04619.102B0545; Wed, 29 Oct 2014 09:23:13 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NE700DWE8QECT50@eusync1.samsung.com>; Wed, 29 Oct 2014 09:23:13 +0000 (GMT) From: Marek Szyprowski To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Tomasz Figa , Kyungmin Park , Russell King - ARM Linux , Kukjin Kim , lauraa@codeaurora.org, linux-omap@vger.kernel.org, linus.walleij@linaro.org, tony@atomide.com, drake@endlessm.com, loeliger@gmail.com, Mark Rutland Subject: [PATCH v7 8/8] ARM: dts: exynos4: Add nodes for L2 cache controller Date: Wed, 29 Oct 2014 10:23:01 +0100 Message-id: <1414574581-2320-9-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1414574581-2320-1-git-send-email-m.szyprowski@samsung.com> References: <1414574581-2320-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrILMWRmVeSWpSXmKPExsVy+t/xy7qMmwJCDG591LB4NP8xs0Xvgqts Fmeb3rBbbO+cwW4x5c9yJotNj6+xWlzeNYfNYvaSfhaLGef3MVncvsxrcW77FhaLtUfuslss vX6RyWLVrj+MFvuveDnwe6yZt4bRo6W5h83j29dJLB6X+3qZPBZ9z/LYOesuu8eda3vYPDYv qffo27KK0ePzJrkArigum5TUnMyy1CJ9uwSujBWr17MW7Oat6PuS3cDYy93FyMkhIWAise7Y PRYIW0ziwr31bF2MXBxCAksZJRZd+sEEkhAS6GOSuNbqD2KzCRhKdL3tYgOxRQSyJX58m8wC 0sAs0McscX56D3MXIweHsICPxJVZXiA1LAKqEhMXf2IFsXkF3CV2LjnLBrFMTuL/yxVg8zkF PCRWX1jCBrHLXWLj4W62CYy8CxgZVjGKppYmFxQnpeca6hUn5haX5qXrJefnbmKEBPOXHYyL j1kdYhTgYFTi4dXY7R8ixJpYVlyZe4hRgoNZSYR3h3lAiBBvSmJlVWpRfnxRaU5q8SFGJg5O qQbG+N2pzccfPmphlYiz3fR7v0pP8GS2pu9uEw0/SPdqy1k9OjY9um5/f5Wa8H9xtdubuNZF b95acEF31cIvskdOS+rLXa8+/fJUo8e7FfsmnWKwu1Gw4GjYYlW3+AkJPXtmXT/9+li5Xuvi 7lO39/TN3BexzMKxkeWWXlNZ08/KWXpfMoxYhfnYlViKMxINtZiLihMBTPUUykQCAAA= Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tomasz Figa This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos4210.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos4x12.dtsi | 14 ++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 536a747a8632..8b97f10f0926 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -64,6 +64,15 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <2 2 1>; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 50b3c3f51e90..3e806d63e8bb 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -54,6 +54,20 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + clock: clock-controller@10030000 { compatible = "samsung,exynos4412-clock"; reg = <0x10030000 0x20000>;