From patchwork Wed Feb 25 19:04:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 5882841 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3A26F9F373 for ; Wed, 25 Feb 2015 19:05:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3295320383 for ; Wed, 25 Feb 2015 19:05:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CB9AE20382 for ; Wed, 25 Feb 2015 19:05:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753564AbbBYTFn (ORCPT ); Wed, 25 Feb 2015 14:05:43 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:51346 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753596AbbBYTFk (ORCPT ); Wed, 25 Feb 2015 14:05:40 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t1PJ5GBf012695; Wed, 25 Feb 2015 13:05:16 -0600 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1PJ5EXq012975; Wed, 25 Feb 2015 13:05:14 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Wed, 25 Feb 2015 13:05:14 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1PJ4Jog007284; Wed, 25 Feb 2015 13:05:13 -0600 From: Tero Kristo To: , , CC: Subject: [PATCHv3 30/35] ARM: dts: omap4: add system control module node Date: Wed, 25 Feb 2015 21:04:40 +0200 Message-ID: <1424891085-10392-31-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1424891085-10392-1-git-send-email-t-kristo@ti.com> References: <1424891085-10392-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add node for system control module, and move all the existing system control IO space users under this new node as its children. A new node for scm_conf area is also added. DT documentation is also updated by this patch to reflect the existence of system control module nodes, separately of PRCM module. Signed-off-by: Tero Kristo --- .../devicetree/bindings/arm/omap/ctrl.txt | 75 +++++++++++++++++++ .../devicetree/bindings/arm/omap/prcm.txt | 6 -- arch/arm/boot/dts/omap4.dtsi | 76 +++++++++++++------- 3 files changed, 125 insertions(+), 32 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/omap/ctrl.txt diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt new file mode 100644 index 0000000..88b12b5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -0,0 +1,75 @@ +OMAP Control Module bindings + +Control Module contains miscellaneous features under it based on SoC type. +Pincontrol is one common feature, and it has a specialized support +described in [1]. Typically some clock nodes are also under control module. +Syscon is used to share register level access to drivers external to +control module driver itself. + +See [2] for documentation about clock/clockdomain nodes. + +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +[2] Documentation/devicetree/bindings/clock/ti/* + +Required properties: +- compatible: Must be one of: + "ti,am3-scrm" + "ti,am4-scrm" + "ti,dm814-scrm" + "ti,dm816-scrm" + "ti,omap2-scrm" + "ti,omap3-scrm" + "ti,omap4-ctrl" +- reg: Contains Control Module register address range + (base address and length) + +Optional properties: +- clocks: clocks for this module +- clockdomains: clockdomains for this module + +Examples: + +scrm: scrm@48002000 { + compatible = "ti,omap3-scrm", "simple-bus"; + reg = <0x48002000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48002000 0x2000>; + + omap3_pmx_core: pinmux@30 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0x30 0x230>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + scm_conf: tisyscon@270 { + compatible = "syscon"; + reg = <0x270 0x330>; + #address-cells = <1>; + #size-cells = <1>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scrm_clockdomains: clockdomains { + }; +} + +&scrm_clocks { + mcbsp5_mux_fck: mcbsp5_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x02d8>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index 68f96f8..3eb6d7a 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes. Required properties: - compatible: Must be one of: "ti,am3-prcm" - "ti,am3-scrm" "ti,am4-prcm" - "ti,am4-scrm" "ti,omap2-prcm" - "ti,omap2-scrm" "ti,omap3-prm" "ti,omap3-cm" - "ti,omap3-scrm" "ti,omap4-cm1" "ti,omap4-prm" "ti,omap4-cm2" @@ -30,9 +26,7 @@ Required properties: "ti,dra7-cm-core-aon" "ti,dra7-cm-core" "ti,dm814-prcm" - "ti,dm814-scrm" "ti,dm816-prcm" - "ti,dm816-scrm" - reg: Contains PRCM module register address range (base address and length) - clocks: clocks for this module diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 074147c..0bab7ce 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -167,38 +167,62 @@ }; }; + scm: scm@4a002000 { + compatible = "ti,omap4-ctrl", "simple-bus"; + reg = <0x4a002000 0x1000>, + <0x4a30a000 0x1000>, + <0x4a100000 0x1000>, + <0x4a31e000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x4a002000 0x1000>, + <1 0 0x4a30a000 0x1000>, + <2 0 0x4a100000 0x1000>, + <3 0 0x4a31e000 0x1000>; + + scm_conf: tisyscon@0,0 { + compatible = "syscon"; + reg = <0 0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; + + omap4_pmx_core: pinmux@2,40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <2 0x40 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap4_pmx_wkup: pinmux@3,40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <3 0x40 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap4_padconf_global: omap4_padconf_global@2,5a0 { + compatible = "syscon"; + reg = <2 0x5a0 0x170>; + }; + }; + counter32k: counter@4a304000 { compatible = "ti,omap-counter32k"; reg = <0x4a304000 0x20>; ti,hwmods = "counter_32k"; }; - omap4_pmx_core: pinmux@4a100040 { - compatible = "ti,omap4-padconf", "pinctrl-single"; - reg = <0x4a100040 0x0196>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - omap4_pmx_wkup: pinmux@4a31e040 { - compatible = "ti,omap4-padconf", "pinctrl-single"; - reg = <0x4a31e040 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap4_padconf_global: tisyscon@4a1005a0 { - compatible = "syscon"; - reg = <0x4a1005a0 0x170>; - }; - pbias_regulator: pbias_regulator { compatible = "ti,pbias-omap"; reg = <0x60 0x4>;