From patchwork Thu Feb 26 12:49:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 5891951 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AA752BF440 for ; Thu, 26 Feb 2015 12:50:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D38712039E for ; Thu, 26 Feb 2015 12:50:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E1A2F203A1 for ; Thu, 26 Feb 2015 12:50:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753791AbbBZMtx (ORCPT ); Thu, 26 Feb 2015 07:49:53 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:37399 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932211AbbBZMts (ORCPT ); Thu, 26 Feb 2015 07:49:48 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t1QCnl9v026323; Thu, 26 Feb 2015 06:49:47 -0600 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1QCnkQe016712; Thu, 26 Feb 2015 06:49:46 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Thu, 26 Feb 2015 06:49:46 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1QCnUhT030427; Thu, 26 Feb 2015 06:49:45 -0600 From: Tomi Valkeinen To: , CC: Tomi Valkeinen Subject: [PATCH 12/15] OMAPDSS: Add support for MFLAG Date: Thu, 26 Feb 2015 14:49:06 +0200 Message-ID: <1424954949-12801-12-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1424954949-12801-1-git-send-email-tomi.valkeinen@ti.com> References: <1424954949-12801-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP OMAP5 has support for MFLAG feature, which allows DSS to dynamically increase the priority of DISPC's DMA traffic. At the moment we don't have support for it. It was noticed that on DRA7 with high bandwidth use cases we see FIFO underflows. Implementing MFLAG support removed those underflows. Interestingly, on OMAP5 uEVM no such overflows were seen. This patch adds a simple MFLAG implementation, where we use a fixed MFLAG threshold value based on the FIFO size. The thresholds are set to 4/8 of fifo size for low threshold, and 5/8 of fifo size for high threshold. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/dispc.c | 50 +++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c index 6296a3e5124f..6b056d0ce187 100644 --- a/drivers/video/fbdev/omap2/dss/dispc.c +++ b/drivers/video/fbdev/omap2/dss/dispc.c @@ -1305,6 +1305,53 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, } EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds); +static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable) +{ + int bit; + + if (plane == OMAP_DSS_GFX) + bit = 14; + else + bit = 23; + + REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); +} + +static void dispc_ovl_set_mflag_threshold(enum omap_plane plane, + int low, int high) +{ + dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); +} + +static void dispc_init_mflag(void) +{ + int i; + + dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE, + (2 << 0) | /* MFLAG_CTRL = enable */ + (0 << 2)); /* MFLAG_START = disable */ + + for (i = 0; i < dss_feat_get_num_ovls(); ++i) { + u32 size = dispc_ovl_get_fifo_size(i); + u32 unit = dss_feat_get_buffer_size_unit(); + u32 low, high; + + dispc_ovl_set_mflag(i, true); + + /* + * Simulation team suggests below thesholds: + * HT = fifosize * 5 / 8; + * LT = fifosize * 4 / 8; + */ + + low = size * 4 / 8 / unit; + high = size * 5 / 8 / unit; + + dispc_ovl_set_mflag_threshold(i, low, high); + } +} + static void dispc_ovl_set_fir(enum omap_plane plane, int hinc, int vinc, enum omap_color_component color_comp) @@ -3630,6 +3677,9 @@ static void _omap_dispc_initial_config(void) if (dispc.feat->mstandby_workaround) REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); + + if (dss_has_feature(FEAT_MFLAG)) + dispc_init_mflag(); } static const struct dispc_features omap24xx_dispc_feats __initconst = {