@@ -231,7 +231,6 @@
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
- 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
@@ -441,6 +440,12 @@
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
+
+ gpio0_pins: gpio0_pins {
+ pinctrl-single,pins = <
+ 0x26c (PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
+ >;
+ };
};
&i2c0 {
@@ -587,7 +592,23 @@
};
&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_pins>;
status = "okay";
+
+ p23 {
+ gpio-hog;
+ gpios = <23 GPIO_ACTIVE_HIGH>;
+ /* SelEMMCorNAND selects between eMMC and NAND:
+ * Low: NAND
+ * High: eMMC
+ * When changing this line make sure the newly
+ * selected device node is enabled and the previously
+ * selected device node is disabled.
+ */
+ output-low;
+ line-name = "SelEMMCorNAND";
+ };
};
&gpio1 {
On this board either eMMC or NAND can work based on the level of spi2_cs0.gpio0_23. Add a gpio-hog to enable configuration of this pin in the device tree. Move pinmux for spi2_cs0 (SEL_eMMCorNANDn) out of NAND node into gpio0 so it is initialized with gpio0. Signed-off-by: Roger Quadros <rogerq@ti.com> --- arch/arm/boot/dts/am437x-gp-evm.dts | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)