From patchwork Fri Sep 11 12:27:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 7160681 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DC7DABF27D for ; Fri, 11 Sep 2015 12:29:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1317420826 for ; Fri, 11 Sep 2015 12:29:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2003C20844 for ; Fri, 11 Sep 2015 12:29:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753493AbbIKM3M (ORCPT ); Fri, 11 Sep 2015 08:29:12 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:37409 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753483AbbIKM3I (ORCPT ); Fri, 11 Sep 2015 08:29:08 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t8BCScQp018488; Fri, 11 Sep 2015 07:28:38 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8BCScL0000774; Fri, 11 Sep 2015 07:28:38 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Fri, 11 Sep 2015 07:30:42 -0500 Received: from dflp33.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8BCROqG013634; Fri, 11 Sep 2015 07:28:35 -0500 From: Peter Ujfalusi To: , , CC: , , , , , Subject: [PATCH v2 23/23] dmaengine: edma: Read channel mapping support only once from HW Date: Fri, 11 Sep 2015 15:27:22 +0300 Message-ID: <1441974442-8233-24-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1441974442-8233-1-git-send-email-peter.ujfalusi@ti.com> References: <1441974442-8233-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of directly reading it from CCCFG register take the information out once when we set up the configuration from the HW. Signed-off-by: Peter Ujfalusi --- drivers/dma/edma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 5fd5cf924daf..bcb3404058cf 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -223,6 +223,7 @@ struct edma_cc { unsigned num_region; unsigned num_slots; unsigned num_tc; + bool chmap_exist; enum dma_event_q default_queue; bool unused_chan_list_done; @@ -1904,11 +1905,14 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, value = GET_NUM_EVQUE(cccfg); ecc->num_tc = value + 1; + ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; + dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); dev_dbg(dev, "num_region: %u\n", ecc->num_region); dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); + dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); /* Nothing need to be done if queue priority is provided */ if (pdata->queue_priority_mapping) @@ -2198,7 +2202,7 @@ static int edma_probe(struct platform_device *pdev) queue_priority_mapping[i][1]); /* Map the channel to param entry if channel mapping logic exist */ - if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + if (ecc->chmap_exist) edma_direct_dmach_to_param_mapping(ecc); for (i = 0; i < ecc->num_region; i++) { @@ -2268,7 +2272,7 @@ static int edma_pm_resume(struct device *dev) queue_priority_mapping[i][1]); /* Map the channel to param entry if channel mapping logic */ - if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + if (ecc->chmap_exist) edma_direct_dmach_to_param_mapping(ecc); for (i = 0; i < ecc->num_channels; i++) {