From patchwork Wed Oct 14 11:42:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 7393021 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 56B379F37F for ; Wed, 14 Oct 2015 11:49:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7A19D206F0 for ; Wed, 14 Oct 2015 11:49:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8A4B1207C1 for ; Wed, 14 Oct 2015 11:49:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753592AbbJNLoj (ORCPT ); Wed, 14 Oct 2015 07:44:39 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:38798 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932421AbbJNLog (ORCPT ); Wed, 14 Oct 2015 07:44:36 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t9EBi3CS017710; Wed, 14 Oct 2015 06:44:03 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t9EBi2HY006001; Wed, 14 Oct 2015 06:44:03 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Wed, 14 Oct 2015 06:44:03 -0500 Received: from dflp32.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t9EBh94w002537; Wed, 14 Oct 2015 06:44:00 -0500 From: Peter Ujfalusi To: , , CC: , , , , , Subject: [PATCH v5 15/24] dmaengine: edma: Use dev_dbg instead pr_debug Date: Wed, 14 Oct 2015 14:42:57 +0300 Message-ID: <1444822986-20562-16-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1444822986-20562-1-git-send-email-peter.ujfalusi@ti.com> References: <1444822986-20562-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We have access to dev, so it is better to use the dev_dbg for debug prints. Signed-off-by: Peter Ujfalusi --- drivers/dma/edma.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index a9fe5c92451d..08f9bd0aa0b3 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -676,23 +676,23 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) /* EDMA channels without event association */ if (test_bit(channel, ecc->edma_unused)) { - pr_debug("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_ESR, j)); + dev_dbg(ecc->dev, "ESR%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ESR, j)); edma_shadow0_write_array(ecc, SH_ESR, j, mask); return 0; } /* EDMA channel with event association */ - pr_debug("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_ER, j)); + dev_dbg(ecc->dev, "ER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ER, j)); /* Clear any pending event or error */ edma_write_array(ecc, EDMA_ECR, j, mask); edma_write_array(ecc, EDMA_EMCR, j, mask); /* Clear any SER */ edma_shadow0_write_array(ecc, SH_SECR, j, mask); edma_shadow0_write_array(ecc, SH_EESR, j, mask); - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); return 0; } @@ -730,8 +730,8 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel) /* clear possibly pending completion interrupt */ edma_shadow0_write_array(ecc, SH_ICR, j, mask); - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); /* REVISIT: consider guarding against inappropriate event * chaining by overwriting with dummy_paramset. @@ -800,8 +800,8 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); - pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), - edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); + dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), + edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); return 0; } @@ -831,8 +831,8 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) int j = (channel >> 5); unsigned int mask = BIT(channel & 0x1f); - pr_debug("EDMA: EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); + dev_dbg(ecc->dev, "EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); edma_shadow0_write_array(ecc, SH_ECR, j, mask); /* Clear the corresponding EMR bits */ edma_write_array(ecc, EDMA_EMCR, j, mask);