From patchwork Tue Mar 1 13:44:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 8465361 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 34E589F8A8 for ; Tue, 1 Mar 2016 13:45:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0F349202C8 for ; Tue, 1 Mar 2016 13:45:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2F27920295 for ; Tue, 1 Mar 2016 13:45:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753746AbcCANo7 (ORCPT ); Tue, 1 Mar 2016 08:44:59 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:41635 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752636AbcCANo6 (ORCPT ); Tue, 1 Mar 2016 08:44:58 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u21DitnV000517; Tue, 1 Mar 2016 07:44:55 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u21DitpE007074; Tue, 1 Mar 2016 07:44:55 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Tue, 1 Mar 2016 07:44:54 -0600 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u21Dios8010748; Tue, 1 Mar 2016 07:44:53 -0600 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [PATCH 1/2] ARM: dts: dm814x: dra62x: Fix NAND device nodes Date: Tue, 1 Mar 2016 15:44:47 +0200 Message-ID: <1456839888-6244-2-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1456839888-6244-1-git-send-email-rogerq@ti.com> References: <1456839888-6244-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dm8148-evm.dts | 7 ++++++- arch/arm/boot/dts/dm814x.dtsi | 2 ++ arch/arm/boot/dts/dra62x-j5eco-evm.dts | 7 ++++++- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index 862977f..be56c8f 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "dm814x.dtsi" +#include / { model = "DM8148 EVM"; @@ -39,8 +40,12 @@ ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ nand@0,0 { - linux,mtd-name= "micron,mt29f2g16aadwp"; + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name= "micron,mt29f2g16aadwp"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index f752ac1..4a6ce8c 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -566,6 +566,8 @@ gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; }; }; }; diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index 3937a58..b0c8144 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "dra62x.dtsi" +#include / { model = "DRA62x J5 Eco EVM"; @@ -39,8 +40,12 @@ ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ nand@0,0 { - linux,mtd-name= "micron,mt29f2g16aadwp"; + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name= "micron,mt29f2g16aadwp"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8";